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Subject: Re: [Qemu-devel] [Bug 1344320] Re: qemu-aarch64 cannot execute glibc
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Richard Earnshaw <rearnsha@arm.com>

On 07/22/2014 12:22 PM, Peter Maydell wrote:
> In any case the kernel guys say you can't guarantee they
> exist unless you get them to define an ELF hwcap for
> "timers exist and have a sane value in the 'what frequency
> are they' register". So this is a glibc bug and I'm
> not fixing QEMU...

There seems to be a bit of confusion in the manual:

In the Preface:

# Chapter D7 The Generic Timer
# Read this for a description of an implementation of the ARM Generic Timer,
that is an extension to
# an ARMv8 PE implementation.

Section A1.3.3:

# The System registers comprise:
# General system control registers.
# Debug registers.
# Generic Timer registers.
# Optionally, Performance Monitor registers.
# Optionally, Trace registers.
# Optionally, Generic Interrupt Controller (GIC) CPU interface registers.

Note that there are 3 sections marked "optional", but not including the timer.

So which is true: typo here in A1.3.3 or are the GT registers required to exist?


r~