From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40572) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XC6iV-0006Cp-Mq for qemu-devel@nongnu.org; Tue, 29 Jul 2014 08:41:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XC6iP-0001W8-E1 for qemu-devel@nongnu.org; Tue, 29 Jul 2014 08:41:19 -0400 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]:41932) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XC6iP-0001Vn-6d for qemu-devel@nongnu.org; Tue, 29 Jul 2014 08:41:13 -0400 Received: by mail-pa0-f54.google.com with SMTP id fa1so12363936pad.13 for ; Tue, 29 Jul 2014 05:41:12 -0700 (PDT) Message-ID: <53D79664.9070007@gmail.com> Date: Tue, 29 Jul 2014 20:41:08 +0800 From: Elta MIME-Version: 1.0 References: <1406563102-11035-1-git-send-email-elta.era@gmail.com> <1406563102-11035-2-git-send-email-elta.era@gmail.com> <20140728214242.GA24813@ohm.rr44.fr> <20140728223236.GC18733@ohm.rr44.fr> <20140728225254.GA1268@hall.aurel32.net> In-Reply-To: <20140728225254.GA1268@hall.aurel32.net> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips/translate.c: Add judgement for msb and lsb List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno , Peter Maydell Cc: QEMU Developers On 07/29/2014 06:52 AM, Aurelien Jarno wrote: > On Mon, Jul 28, 2014 at 11:34:30PM +0100, Peter Maydell wrote: >> On 28 July 2014 23:32, Aurelien Jarno wrote: >>> On Mon, Jul 28, 2014 at 11:01:02PM +0100, Peter Maydell wrote: >>>> This may be true, but the TCG README doesn't define negative >>>> lengths as being "unspecified behaviour" (ie guaranteed to at >>>> least not crash even if the result isn't specified), and in fact the >>>> implementation of tcg_gen_deposit will assert on negative lengths. >>>> We shouldn't implement guest unpredictable cases as "crash QEMU". >>> Well I tried this code under QEMU, and it clearly doesn't crash. It >>> seems the assert are not enabled with the default configuration options. >> Try --enable-debug... > That's my point, it's only in debug mode, not in the default > configuration. Maybe remove the tcg_debug_assert in tcg_gen_deposit_i64 and tcg_gen_deposit_i64 is a better way. But it may cause other mistake in other architecture, i'm not sure. > >>> That said I agree it's something to avoid, but I don't think triggering >>> a RI exception is the thing to do (even if it is correct according the >>> MIPS ISA manual) when real silicon output a random result instead. >> Yes, you could emit code to do that instead if you like. > When I said random, it didn't say in the sense of random generator, but > in the sense a result that might depend on the input value and the > silicon implementation. It would be silly to emit code just for that, > but it would be smart for example to skip the deposit op in that case > instead of triggering an exception. > I think, debug mode shouldn't crash the qemu with an unpredictable operation, so i want to fix it. And you say there shouldn't raise RI, i agree with you. Or when lsb > msb, just leave the code and do nothing. What do you think about this way?