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Sender: Richard Henderson <rth7680@gmail.com>
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Subject: Re: [Qemu-devel] [PATCH v3 07/15] target-tricore: Add instructions
 of SRR opcode format
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org

On 08/04/2014 07:38 AM, Bastian Koppelmann wrote:
> +target_ulong helper_add_ssov(CPUTRICOREState *env, target_ulong r1,
> +                             target_ulong r2)
> +{
> +    target_ulong ret;
> +    int64_t result = (int64_t)r1 + (int64_t)r2;
> +    SSOV(env, ret, result, 32);
> +    return ret;
> +}
> +
> +target_ulong helper_sub_ssov(CPUTRICOREState *env, target_ulong r1,
> +                             target_ulong r2)
> +{
> +    target_ulong ret;
> +    int64_t result = (int64_t)r1 - (int64_t)r2;
> +    SSOV(env, ret, result, 32);
> +    return ret;
> +}
> +

This zero-extends r1 and r2; you need to sign-extend in order for your
saturation to work.

> +    tcg_gen_sub2_tl(ret, cpu_PSW_V, r1, t0, r2, t0);
> +    gen_calc_psw_sv_i32(cpu_PSW_SV, cpu_PSW_V);

This computes neither carry nor overflow.

> +    /* mul and set V/SV bits */
> +    tcg_gen_muls2_tl(ret, cpu_PSW_V, r1, r2);

Overflow computation requires that you compare the high part of the result vs
the sign of the low part of the result.  I.e.

	overflow = (high != (low >> 31));


r~