From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54164) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XENqf-0003Aj-2P for qemu-devel@nongnu.org; Mon, 04 Aug 2014 15:23:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XENqV-0007Ve-OS for qemu-devel@nongnu.org; Mon, 04 Aug 2014 15:23:09 -0400 Received: from mail-qa0-x232.google.com ([2607:f8b0:400d:c00::232]:36027) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XENqV-0007VU-BT for qemu-devel@nongnu.org; Mon, 04 Aug 2014 15:22:59 -0400 Received: by mail-qa0-f50.google.com with SMTP id s7so7253977qap.37 for ; Mon, 04 Aug 2014 12:22:58 -0700 (PDT) Sender: Richard Henderson Message-ID: <53DFDD8E.70203@twiddle.net> Date: Mon, 04 Aug 2014 09:22:54 -1000 From: Richard Henderson MIME-Version: 1.0 References: <1407173932-969-1-git-send-email-kbastian@mail.uni-paderborn.de> <1407173932-969-16-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1407173932-969-16-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 15/15] target-tricore: Add instructions of SR opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org > + case OPC2_16_SR_RSUB: > + /* overflow only if r1 = -0x80000000 */ > + temp = tcg_const_i32(-0x80000000); > + t0 = tcg_const_i32(0); > + t1 = tcg_const_i32(1); > + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp, t1, t0); This is setcond. > + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_PSW_SV, cpu_gpr_d[r1], temp, > + t1, cpu_PSW_SV); This is or of the setcond. r~