From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF7sp-00036S-5r for qemu-devel@nongnu.org; Wed, 06 Aug 2014 16:32:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XF7sg-0001Cb-4z for qemu-devel@nongnu.org; Wed, 06 Aug 2014 16:32:27 -0400 Received: from mail-qg0-x233.google.com ([2607:f8b0:400d:c04::233]:59166) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XF7sg-0001CR-0i for qemu-devel@nongnu.org; Wed, 06 Aug 2014 16:32:18 -0400 Received: by mail-qg0-f51.google.com with SMTP id a108so3410677qge.10 for ; Wed, 06 Aug 2014 13:32:17 -0700 (PDT) Sender: Richard Henderson Message-ID: <53E290CA.4040204@twiddle.net> Date: Wed, 06 Aug 2014 10:32:10 -1000 From: Richard Henderson MIME-Version: 1.0 References: <1406733627-24255-1-git-send-email-alex.bennee@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 0/5] AArch64 TLB performance improvements List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , =?UTF-8?B?QWxleCBCZW5uw6ll?= Cc: QEMU Developers On 08/01/2014 12:26 PM, Peter Maydell wrote: > So I think it would be good if we investigated the degree > of difficulty in improving QEMU's TLB code so it isn't just > "one TLB entry size with larger pages a bolt-on which we > hope people don't actually use" first, before we just disable > all the v5 CPUs. I suspect the overhead of making the guest page size variable will be less than the improvement that can be had in doing so. Supporting multiple page sizes simultaneously, as with "huge pages", is probably unfeasible. r~