From: Eric Blake <eblake@redhat.com>
To: "Jaume Martí" <jaume.martif@gmail.com>,
qemu-devel@nongnu.org, "riku.voipio" <riku.voipio@iki.fi>,
mtosatti@redhat.com, pbonzini@redhat.com, afaerber@suse.de,
mst <mst@redhat.com>,
gleb@redhat.com, "alex.bennee" <alex.bennee@linaro.org>,
anthony <anthony@codemonkey.ws>,
quintela@redhat.com, vrozenfe@redhat.com,
"Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH 0/7] target-i386: x87 exception pointers using TCG.
Date: Wed, 06 Aug 2014 15:38:04 -0600 [thread overview]
Message-ID: <53E2A03C.1020701@redhat.com> (raw)
In-Reply-To: <CAL4g94T+45+W9aYjWyzUgLzyXJTZqoSu1gXLgW34nnBGjYC+AQ@mail.gmail.com>
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On 08/06/2014 02:46 PM, Jaume Martí wrote:
> Hello,
>
> I submit a patch to fix bugs 661696 and 1248376.
> I already submitted a previous version of this patch, this version requires
> less TCG operations to execute.
If this is a second version of the patch, then you should have v2 in the
subject line ('git send-email -v2' is your friend).
> As mentioned in a previous email, the patch implements, for TCG, the
> specifications provided in Intel and AMD programmer's manuals regarding the
> x87 exception pointers. That is, when executing instructions
> fstenv/fnstenv, fsave and fxsave the values for the instruction pointer,
> data pointer and opcode of the last non-control x87 instruction executed,
> are correctly saved to the specified memory address. When executing
> instructions fldenv, frstor and fxrstor the values that are going to be
> considered the instruction pointer, data pointer and opcode of the last
> non-control x87 instruction are obtained from the specified memory address.
>
> I divided this patch in 8 parts, this first part involves changes in the
> CPUX86State struct to store the exception pointers.
Huh? This mail is titled 0/7, so I only expect 7 parts. Oh...
>
> Best regards,
> Jaume
>
> Signed-off-by: Jaume Marti Farriol (jaume.martif@gmail.com)
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index e634d83..4274ce3 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
...reviewers don't expect to see patch contents in the cover letter. If
you truly have eight parts, then they should be numbered 1/8 through
8/8, and this cover letter 0/8 should contain only a diffstat summary of
those 8 patches.
Furthermore, your threading appears to be wrong - your remaining patches
each start their own thread instead of being in reply to this cover
letter. Please make sure you set In-Reply-To headers correctly when
sending a series.
http://wiki.qemu.org/Contribute/SubmitAPatch has more hints on how to
send a patch series.
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
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prev parent reply other threads:[~2014-08-06 21:38 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-06 20:46 [Qemu-devel] [PATCH 0/7] target-i386: x87 exception pointers using TCG Jaume Martí
2014-08-06 21:38 ` Eric Blake [this message]
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