From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:36607)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1XFZvf-0007Bx-1M
	for qemu-devel@nongnu.org; Thu, 07 Aug 2014 22:29:24 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1XFZvV-0007tO-Vs
	for qemu-devel@nongnu.org; Thu, 07 Aug 2014 22:29:14 -0400
Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]:44170)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1XFZvV-0007tE-Nt
	for qemu-devel@nongnu.org; Thu, 07 Aug 2014 22:29:05 -0400
Received: by mail-pd0-f174.google.com with SMTP id fp1so6236803pdb.33
	for <qemu-devel@nongnu.org>; Thu, 07 Aug 2014 19:29:03 -0700 (PDT)
Sender: Richard Henderson <rth7680@gmail.com>
Message-ID: <53E435EA.3070408@twiddle.net>
Date: Thu, 07 Aug 2014 16:28:58 -1000
From: Richard Henderson <rth@twiddle.net>
MIME-Version: 1.0
References: <1407422081-9468-1-git-send-email-kbastian@mail.uni-paderborn.de>
	<1407422081-9468-2-git-send-email-kbastian@mail.uni-paderborn.de>
In-Reply-To: <1407422081-9468-2-git-send-email-kbastian@mail.uni-paderborn.de>
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs
 and qom-cpu
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org

On 08/07/2014 04:34 AM, Bastian Koppelmann wrote:
> +    /* PSW flag cache for faster execution
> +       if flag != 0 then flag is set. Else flag is not set.
> +    */
> +    target_ulong PSW_USB_C;
> +    target_ulong PSW_USB_V;
> +    target_ulong PSW_USB_SV;
> +    target_ulong PSW_USB_AV;  /* Only if bit 31 set, then flag is set. */
> +    target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */

V and SV are also only set if bit 31 is set, the way we're computing overflow
from addition.  Of course, overflow from saturation or multiplication isn't
being computed into bit 31, so there is a decision to make.

Depending on how important it is for ADDX+ADDC to be implemented efficiently,
vs how important is for SHA to be quick, you may wish to have C already set to
0/1 only.


r~