From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XFhT2-0003ns-2f for qemu-devel@nongnu.org; Fri, 08 Aug 2014 06:32:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XFhSv-0000hh-RH for qemu-devel@nongnu.org; Fri, 08 Aug 2014 06:32:12 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:35283) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XFhSv-0000hI-LO for qemu-devel@nongnu.org; Fri, 08 Aug 2014 06:32:05 -0400 Message-ID: <53E4B61B.5030608@mail.uni-paderborn.de> Date: Fri, 08 Aug 2014 12:35:55 +0100 From: Bastian Koppelmann MIME-Version: 1.0 References: <1407422081-9468-1-git-send-email-kbastian@mail.uni-paderborn.de> <1407422081-9468-2-git-send-email-kbastian@mail.uni-paderborn.de> <53E435EA.3070408@twiddle.net> <53E4A909.7080902@mail.uni-paderborn.de> In-Reply-To: <53E4A909.7080902@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 01/15] target-tricore: Add target stubs and qom-cpu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 08/08/2014 11:40 AM, Bastian Koppelmann wrote: > > On 08/08/2014 03:28 AM, Richard Henderson wrote: >> On 08/07/2014 04:34 AM, Bastian Koppelmann wrote: >>> + /* PSW flag cache for faster execution >>> + if flag != 0 then flag is set. Else flag is not set. >>> + */ >>> + target_ulong PSW_USB_C; >>> + target_ulong PSW_USB_V; >>> + target_ulong PSW_USB_SV; >>> + target_ulong PSW_USB_AV; /* Only if bit 31 set, then flag is >>> set. */ >>> + target_ulong PSW_USB_SAV; /* Only if bit 31 set, then flag is >>> set. */ >> V and SV are also only set if bit 31 is set, the way we're computing >> overflow >> from addition. Of course, overflow from saturation or multiplication >> isn't >> being computed into bit 31, so there is a decision to make. > I would not define V and SV as bit 31. It would not change the > generation of add/sub insn, but adds additional tcg insn to mul and > saturation. It would just help the psw_write/_read helpers, which are > not that often called. But maybe I'm missing future insn that might > benefit :). Never mind. I see the problem now. The computation of the V bit for add/sub insn will set more than just the 31 bit. So I would choose to define it as bit 31, to benefit the more common add/sub insn. >> Depending on how important it is for ADDX+ADDC to be implemented >> efficiently, >> vs how important is for SHA to be quick, you may wish to have C >> already set to >> 0/1 only. >> >> >> r~ > >