From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XINYQ-0003pP-C7 for qemu-devel@nongnu.org; Fri, 15 Aug 2014 15:52:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XINYG-0001ff-4P for qemu-devel@nongnu.org; Fri, 15 Aug 2014 15:52:50 -0400 Sender: Richard Henderson Message-ID: <53EE64FD.4090305@twiddle.net> Date: Fri, 15 Aug 2014 09:52:29 -1000 From: Richard Henderson MIME-Version: 1.0 References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> <1407785009-6538-2-git-send-email-tommusta@gmail.com> <53EE52A4.70806@twiddle.net> In-Reply-To: <53EE52A4.70806@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/8] target-ppc: Bug Fix: rlwinm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: agraf@suse.de On 08/15/2014 08:34 AM, Richard Henderson wrote: > On 08/11/2014 09:23 AM, Tom Musta wrote: >> The rlwinm specification includes the ROTL32 operation, which is defined >> to be a left rotation of two copies of the least significant 32 bits of >> the source GPR. >> >> The current implementation is incorrect on 64-bit implementations in that >> it rotates a single copy of the least significant 32 bits, padding with >> zeroes in the most significant bits. > > Yes, it does describe rotate_32 as a double-copy of the low 32 bits. But it > also describes the mask as having "0 bits elsewhere". Thus, post mask, I don't > see how you could distinguish the implementations. > > Have you an example that doesn't work with the current code? Let me guess the answer myself -- it's MB > ME, and wraparound of the mask. I think I was distracted by the text "For all the uses given above, the high-order 32 bits of register RA are cleared." without clearly reading the examples. r~