From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XINlT-0007Fq-3s for qemu-devel@nongnu.org; Fri, 15 Aug 2014 16:06:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XINlI-0005mQ-Ix for qemu-devel@nongnu.org; Fri, 15 Aug 2014 16:06:19 -0400 Sender: Richard Henderson Message-ID: <53EE6825.5040706@twiddle.net> Date: Fri, 15 Aug 2014 10:05:57 -1000 From: Richard Henderson MIME-Version: 1.0 References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> <1407785009-6538-4-git-send-email-tommusta@gmail.com> In-Reply-To: <1407785009-6538-4-git-send-email-tommusta@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 3/8] target-ppc: Bug Fix: rlwimi List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: agraf@suse.de On 08/11/2014 09:23 AM, Tom Musta wrote: > Also fix the special case of MB=31 and ME=0 to copy the entire contents > of the source GPR. Err, that's not what you did. > if (likely(sh == 0 && mb == 0 && me == 31)) { > +#if defined(TARGET_PPC64) > + tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > +#else > tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > +#endif This is the reverse condition. Which, true enough, should not be implemented with ext32u for PPC64. But a MOV isn't right either, it is deposit(ra, rs, 0, 32) Which does point out that we should probably implement anything MB <= ME and SH == 31 - ME with the deposit opcode. r~