From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XINqy-0005w8-Sd for qemu-devel@nongnu.org; Fri, 15 Aug 2014 16:12:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XINqp-0007SL-S1 for qemu-devel@nongnu.org; Fri, 15 Aug 2014 16:12:00 -0400 Sender: Richard Henderson Message-ID: <53EE697F.500@twiddle.net> Date: Fri, 15 Aug 2014 10:11:43 -1000 From: Richard Henderson MIME-Version: 1.0 References: <1407785009-6538-1-git-send-email-tommusta@gmail.com> <1407785009-6538-6-git-send-email-tommusta@gmail.com> In-Reply-To: <1407785009-6538-6-git-send-email-tommusta@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 5/8] target-ppc: Bug Fix: mullwo List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: agraf@suse.de On 08/11/2014 09:23 AM, Tom Musta wrote: > tcg_gen_muls2_i32(t0, t1, t0, t1); > tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); > +#if defined(TARGET_PPC64) > + tcg_gen_ext_i32_tl(t2, t1); > + tcg_gen_deposit_i64(cpu_gpr[rD(ctx->opcode)], > + cpu_gpr[rD(ctx->opcode)], t2, 32, 32); > + tcg_temp_free(t2); > +#endif This is tcg_gen_muls2_i32(t0, t0, t0, t1); #if defined(TARGET_PPC64) tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); #else tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); #endif r~