From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55627) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XK5Xg-0001bh-OX for qemu-devel@nongnu.org; Wed, 20 Aug 2014 09:03:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XK5Xb-0002BV-Q2 for qemu-devel@nongnu.org; Wed, 20 Aug 2014 09:03:08 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:18787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XK5Xb-0002Ao-Fd for qemu-devel@nongnu.org; Wed, 20 Aug 2014 09:03:03 -0400 Message-ID: <53F4AB80.5000904@mail.uni-paderborn.de> Date: Wed, 20 Aug 2014 15:06:56 +0100 From: Bastian Koppelmann MIME-Version: 1.0 References: <1407931644-25602-1-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1407931644-25602-1-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 00/15] TriCore architecture guest implementation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net ping, anyone? Patchwork links: 01: https://patchwork.ozlabs.org/patch/379594/ 02: https://patchwork.ozlabs.org/patch/379598/ 03: https://patchwork.ozlabs.org/patch/379600/ 04: https://patchwork.ozlabs.org/patch/379588/ 05: https://patchwork.ozlabs.org/patch/379589/ 06: https://patchwork.ozlabs.org/patch/379591/ 07: https://patchwork.ozlabs.org/patch/379587/ 08: https://patchwork.ozlabs.org/patch/379596/ 09: https://patchwork.ozlabs.org/patch/379597/ 10: https://patchwork.ozlabs.org/patch/379592/ 11: https://patchwork.ozlabs.org/patch/379593/ 12: https://patchwork.ozlabs.org/patch/379595/ 13: https://patchwork.ozlabs.org/patch/379586/ 14: https://patchwork.ozlabs.org/patch/379590/ 15: https://patchwork.ozlabs.org/patch/379599/ Thanks, Bastian On 08/13/2014 01:07 PM, Bastian Koppelmann wrote: > Hi, > > my aim is to add Infineon's TriCore architecture to QEMU. This series of patches adds the target stubs, a basic testboard and a softmmu for system mode emulation. Furthermore it adds all the 16 bit long instructions of the architecture grouped by opcode format. > > After this series of patches. Another one will follow, which adds a lot of the 32 bit long instructions. > > All the best > > Bastian > > v4 -> v5: > - Change documentation of S, SV bits to use bit 31. > - psw_read/_write now uses only bit 31 of S, SV bits. > - gen_intermediate_code_internal: Move calculation of next_pc after the ifs for singlestep and long tbs. > - gen_shaci: Change case of shift_count == 32 to shift_count == -32 and add the clear of V bit. > - gen_shaci: Move creation and freeing of t_max, t_min to case shift_count > 0. > - gen_shaci: Add cast to int32_t to the creation of t_min. > - gen_shaci: Now msk is 1 bit longer and uses a positive value of shift_count in the else case. > - gen_shaci: now computes V bit in bit 31. > - gen_shaci: Move computation of shift after the computation of PSW bits to handle the case of ret = r1. > - gen_shaci: Add clear of V bit for cases shift_count = 0 / = -32 / < 0. > - gen_add_d now saves result of addition into tcg temp to handle ret = r1 cases. > - gen_cond_add now sets SV, SAV bits conditionally. > - gen_cond_add now writes result after PSW bit computations, to handle ret = r1 cases. > - Change int cond to TCGCond on function gen_cond_add, gen_condi_add. > - Switched source and destination register of SRC_ADD_A15 and SRC_ADD_15A insns. > - Negate conditions of 16_SRC_CMOV and 16_SRC_CMOVN insns. > - SRC_MOV_A loads const4 zero extended. (Googled alot to find a manual saying it should be sign extended, but couldn't. 1.3 and 1.6 manual state sign extension) > - RSUB now computes V bit in bit 31. > - gen_sub_d now saves result of substraction into tcg temp to handle ret = r1 cases. > - gen_mul_i32s now calculates V, SV bits in bit 31. > - SSOV makro now computes V, SV bits in bit 31. > - Negate conditions of 16_SRR_CMOV and 16_SRR_CMOVN insns. > - MOV_AA: Switch r1 and r2 arguments. > - decode_16Bit_opc: Add if to handle ADDSC.A opcode being 6 bit instead of 7 bit long. > - Change int cond to TCGCond in functions gen_branch_cond, gen_branch_condi. > - gen_intermediate_code_internal: Add gen_goto_tb so qemu finds new tb on singlestep and after long tbs without branch. > - Switched sat_neg and arg in first movcond in function gen_saturate. > - SR_NOT: Remove if checking OP2. > > > Bastian Koppelmann (15): > target-tricore: Add target stubs and qom-cpu > target-tricore: Add board for systemmode > target-tricore: Add softmmu support > target-tricore: Add initialization for translation and activate target > target-tricore: Add masks and opcodes for decoding > target-tricore: Add instructions of SRC opcode format > target-tricore: Add instructions of SRR opcode format > target-tricore: Add instructions of SSR opcode format > target-tricore: Add instructions of SRRS and SLRO opcode format > target-tricore: Add instructions of SB opcode format > target-tricore: Add instructions of SBC and SBRN opcode format > target-tricore: Add instructions of SBR opcode format > target-tricore: Add instructions of SC opcode format > target-tricore: Add instructions of SLR, SSRO and SRO opcode format > target-tricore: Add instructions of SR opcode format > > arch_init.c | 2 + > configure | 5 + > cpu-exec.c | 11 +- > cpus.c | 6 + > default-configs/tricore-softmmu.mak | 3 + > hw/tricore/Makefile.objs | 1 + > hw/tricore/tricore_testboard.c | 129 ++++ > include/elf.h | 2 + > include/hw/tricore/tricore.h | 54 ++ > include/sysemu/arch_init.h | 1 + > target-tricore/Makefile.objs | 1 + > target-tricore/cpu-qom.h | 71 ++ > target-tricore/cpu.c | 191 +++++ > target-tricore/cpu.h | 400 ++++++++++ > target-tricore/helper.c | 144 ++++ > target-tricore/helper.h | 25 + > target-tricore/op_helper.c | 392 ++++++++++ > target-tricore/translate.c | 1259 +++++++++++++++++++++++++++++++ > target-tricore/tricore-defs.h | 28 + > target-tricore/tricore-opcodes.h | 1406 +++++++++++++++++++++++++++++++++++ > 20 files changed, 4130 insertions(+), 1 deletion(-) > create mode 100644 default-configs/tricore-softmmu.mak > create mode 100644 hw/tricore/Makefile.objs > create mode 100644 hw/tricore/tricore_testboard.c > create mode 100644 include/hw/tricore/tricore.h > create mode 100644 target-tricore/Makefile.objs > create mode 100644 target-tricore/cpu-qom.h > create mode 100644 target-tricore/cpu.c > create mode 100644 target-tricore/cpu.h > create mode 100644 target-tricore/helper.c > create mode 100644 target-tricore/helper.h > create mode 100644 target-tricore/op_helper.c > create mode 100644 target-tricore/translate.c > create mode 100644 target-tricore/tricore-defs.h > create mode 100644 target-tricore/tricore-opcodes.h >