From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54706) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKZ2H-0008RH-8L for qemu-devel@nongnu.org; Thu, 21 Aug 2014 16:32:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XKZ28-0005Xz-78 for qemu-devel@nongnu.org; Thu, 21 Aug 2014 16:32:41 -0400 Received: from mail-qc0-x229.google.com ([2607:f8b0:400d:c01::229]:38779) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XKZ28-0005Wf-3H for qemu-devel@nongnu.org; Thu, 21 Aug 2014 16:32:32 -0400 Received: by mail-qc0-f169.google.com with SMTP id c9so10089816qcz.28 for ; Thu, 21 Aug 2014 13:32:30 -0700 (PDT) Sender: Richard Henderson Message-ID: <53F65759.6020604@twiddle.net> Date: Thu, 21 Aug 2014 13:32:25 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1407931644-25602-1-git-send-email-kbastian@mail.uni-paderborn.de> <1407931644-25602-7-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1407931644-25602-7-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 06/15] target-tricore: Add instructions of SRC opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 08/13/2014 05:07 AM, Bastian Koppelmann wrote: > +static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) > +{ > + uint32_t msk, msk_start; > + TCGv temp = tcg_temp_new(); > + TCGv temp2 = tcg_temp_new(); > + TCGv t_0 = tcg_const_i32(0); > + > + if (shift_count == 0) { > + /* Clear PSW.C and PSW.V */ > + tcg_gen_movi_tl(cpu_PSW_C, 0); > + tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); > + tcg_gen_mov_tl(ret, r1); > + } else if (shift_count == -32) { > + /* fill ret completly with sign bit */ > + tcg_gen_sari_tl(ret, r1, 31); > + /* clear PSW.V */ > + tcg_gen_movi_tl(cpu_PSW_V, 0); You've forgotten to set C here. I think it's just tcg_gen_mov_tl(cpu_PSW_C, r1); Of course, you need to do that before writing to ret. > + } else if (shift_count > 0) { > + TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); > + TCGv t_min = tcg_const_i32(((int32_t)(-0x80000000)) >> shift_count); > + > + /* calc carry */ > + msk_start = 32 - shift_count; > + msk = ((1 << shift_count) - 1) << msk_start; > + tcg_gen_andi_tl(cpu_PSW_C, r1, msk); > + /* calc v/sv bits */ > + tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); > + tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); > + tcg_gen_or_tl(cpu_PSW_V, temp, temp2); > + tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); > + /* calc sv */ > + tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); > + /* do shift */ > + tcg_gen_shli_tl(ret, r1, shift_count); > + > + tcg_temp_free(t_max); > + tcg_temp_free(t_min); > + } else { > + /* clear PSW.V */ > + tcg_gen_movi_tl(cpu_PSW_V, 0); > + /* calc carry */ > + msk = (1 << (-shift_count)) - 1; > + tcg_gen_andi_tl(cpu_PSW_C, r1, msk); > + /* do shift */ > + tcg_gen_sari_tl(ret, r1, -(shift_count)); > + } Please avoid useless parenthesis, like -(x) and (-x). r~