From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40332) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XLqRu-0006xg-2i for qemu-devel@nongnu.org; Mon, 25 Aug 2014 05:20:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XLqRo-00045B-Ha for qemu-devel@nongnu.org; Mon, 25 Aug 2014 05:20:26 -0400 Received: from mail-lb0-x231.google.com ([2a00:1450:4010:c04::231]:61204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XLqRo-00044g-Al for qemu-devel@nongnu.org; Mon, 25 Aug 2014 05:20:20 -0400 Received: by mail-lb0-f177.google.com with SMTP id s7so11586311lbd.8 for ; Mon, 25 Aug 2014 02:20:19 -0700 (PDT) Message-ID: <53FAFFD2.7070208@gmail.com> Date: Mon, 25 Aug 2014 13:20:18 +0400 From: Sergey Fedorov MIME-Version: 1.0 References: <1408703392-23893-1-git-send-email-aggelerf@ethz.ch> <1408703392-23893-4-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1408703392-23893-4-git-send-email-aggelerf@ethz.ch> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 03/15] hw/intc/arm_gic: Add Security Extensions property List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabian Aggeler , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, edgar.iglesias@gmail.com, christoffer.dall@linaro.org, greg.bellows@linaro.org On 22.08.2014 14:29, Fabian Aggeler wrote: > The existing implementation does not support Security Extensions mentioned > in the GICv1 and GICv2 architecture specification. Security Extensions are > not available on all GICs. This property makes it possible to enable Security Extensions. > > It also makes GICD_TYPER/ICDICTR.SecurityExtn RAO for GICs which implement > Security Extensions. > > Signed-off-by: Fabian Aggeler > --- > hw/intc/arm_gic.c | 5 ++++- > hw/intc/arm_gic_common.c | 1 + > include/hw/intc/arm_gic_common.h | 1 + > 3 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index b27bd0e..75b5121 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -297,7 +297,10 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) > if (offset == 0) > return s->enabled; > if (offset == 4) > - return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); > + /* Interrupt Controller Type Register */ > + return ((s->num_irq / 32) - 1) > + | ((NUM_CPU(s) - 1) << 5) > + | (s->security_extn << 10); > if (offset < 0x08) > return 0; > if (offset >= 0x80) { > diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c > index 6d884ec..302a056 100644 > --- a/hw/intc/arm_gic_common.c > +++ b/hw/intc/arm_gic_common.c > @@ -149,6 +149,7 @@ static Property arm_gic_common_properties[] = { > * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) > */ > DEFINE_PROP_UINT32("revision", GICState, revision, 1), > + DEFINE_PROP_UINT8("security-extn", GICState, security_extn, 0), Why don't use bool type and DEFINE_PROP_BOOL for this field? Regards, Sergey. > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h > index 01c6f24..4e25017 100644 > --- a/include/hw/intc/arm_gic_common.h > +++ b/include/hw/intc/arm_gic_common.h > @@ -105,6 +105,7 @@ typedef struct GICState { > MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ > uint32_t num_irq; > uint32_t revision; > + uint8_t security_extn; > int dev_fd; /* kvm device fd if backed by kvm vgic support */ > } GICState; >