Re: [Qemu-devel] [PATCH 05/13] Q35: implement property interfece to several parameters

[Paolo Bonzini <pbonzini@redhat.com>]

On 17/06/2016 15:11, Efimov Vasily wrote:
> During creation of Q35 instance several parameters are set using direct access.
> It violates Qemu device model. Correctly, the parameters should be handled as
> object properties.
> 
> The patch adds four link type properties for fields:
> mch.ram_memory
> mch.pci_address_space
> mch.system_memory
> mch.address_space_io
> And, it adds two size type properties for fields:
> mch.below_4g_mem_size
> mch.above_4g_mem_size
> 
> Signed-off-by: Efimov Vasily <real@ispras.ru>
> ---
>  hw/pci-host/q35.c         | 20 ++++++++++++++++++++
>  include/hw/i386/pc.h      |  2 ++
>  include/hw/pci-host/q35.h |  5 +++++
>  3 files changed, 27 insertions(+)
> 
> diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
> index 70f897e..ab337b8 100644
> --- a/hw/pci-host/q35.c
> +++ b/hw/pci-host/q35.c
> @@ -127,6 +127,10 @@ static Property mch_props[] = {
>      DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
>                       mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
>      DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
> +    DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
> +                     mch.below_4g_mem_size, 0),
> +    DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
> +                     mch.above_4g_mem_size, 0),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> @@ -177,6 +181,22 @@ static void q35_host_initfn(Object *obj)
>                          q35_host_get_mmcfg_size,
>                          NULL, NULL, NULL, NULL);
>  
> +    object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
> +            (Object **) &s->mch.ram_memory, object_property_allow_set_link,
> +            0, NULL);
> +
> +    object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
> +            (Object **) &s->mch.pci_address_space,
> +            object_property_allow_set_link, 0, NULL);
> +
> +    object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
> +            (Object **) &s->mch.system_memory, object_property_allow_set_link,
> +            0, NULL);
> +
> +    object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
> +            (Object **) &s->mch.address_space_io,
> +            object_property_allow_set_link, 0, NULL);

This should use qdev_prop_allow_set_link_before_realize.

Paolo

>      /* Leave enough space for the biggest MCFG BAR */
>      /* TODO: this matches current bios behaviour, but
>       * it's not a power of two, which means an MTRR
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index aab3a53..5193ae9 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -238,6 +238,8 @@ void pc_guest_info_init(PCMachineState *pcms);
>  #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
>  #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
>  #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
> +#define PCI_HOST_BELOW_4G_MEM_SIZE     "below-4g-mem-size"
> +#define PCI_HOST_ABOVE_4G_MEM_SIZE     "above-4g-mem-size"
>  #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
>  
>  
> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> index c5c073d..8b4bde3 100644
> --- a/include/hw/pci-host/q35.h
> +++ b/include/hw/pci-host/q35.h
> @@ -78,6 +78,11 @@ typedef struct Q35PCIHost {
>   * gmch part
>   */
>  
> +#define MCH_HOST_PROP_RAM_MEM "ram-mem"
> +#define MCH_HOST_PROP_PCI_MEM "pci-mem"
> +#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
> +#define MCH_HOST_PROP_IO_MEM "io-mem"
> +
>  /* PCI configuration */
>  #define MCH_HOST_BRIDGE                        "MCH"
>  
>