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[201.69.66.211]) by smtp.gmail.com with ESMTPSA id t6-20020a056870180600b001b02a3426ddsm1651597oaf.14.2023.07.21.09.08.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Jul 2023 09:08:43 -0700 (PDT) Message-ID: <53f9edf9-1796-340a-ceb7-4b6ed1963748@gmail.com> Date: Fri, 21 Jul 2023 13:08:40 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v2] target/ppc: Generate storage interrupts for radix RC changes Content-Language: en-US To: Nicholas Piggin , Shawn Anastasio , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Greg Kurz , David Gibson , Timothy Pearson , Frederic Barrat References: <20230712161322.2729950-1-sanastasio@raptorengineering.com> <1004ffbe-8855-75d1-45e7-65360bfd1807@raptorengineering.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=danielhb413@gmail.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/20/23 23:38, Nicholas Piggin wrote: > On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote: >> On 7/12/23 11:56 AM, Cédric Le Goater wrote: >>> Hello Shawn, >>> >>> On 7/12/23 18:13, Shawn Anastasio wrote: >>>> Change radix model to always generate a storage interrupt when the R/C >>>> bits are not set appropriately in a PTE instead of setting the bits >>>> itself. According to the ISA both behaviors are valid, but in practice >>>> this change more closely matches behavior observed on the POWER9 CPU. >>> >>> How did you spotted this dark corner case in emulation ? Do you have >>> MMU unit tests ? >> >> I'm currently porting Xen to Power and have been using QEMU's powernv >> model extensively for early bring up. I noticed the issue when my radix >> implementation worked in QEMU but failed on actual hardware since I >> didn't have a proper storage interrupt handler implemented. > > Cool. This was on my todo list because we rely on it for nested HV > KVM too. > > I actually didn't know about that odd effLIPD=0 exception, but it > looks right. How did you test that, by running with MSR[HV]=0 and > LPIDR=0 ? > > For the patch, > > Reviewed-by: Nicholas Piggin Cedric, do you think this is 8.1 material? Daniel > > Thanks, > Nick