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From: Tom Musta <tommusta@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: dgibson@redhat.com, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr
Date: Wed, 03 Sep 2014 14:41:18 -0500	[thread overview]
Message-ID: <54076EDE.3050208@gmail.com> (raw)
In-Reply-To: <1409246113-6519-12-git-send-email-pbonzini@redhat.com>

On 8/28/2014 12:15 PM, Paolo Bonzini wrote:
> It sets CR1, not CR6 (and the spec agrees).
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  target-ppc/translate.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 8def0ae..67f13f7 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -8179,7 +8179,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg)
>  }
>  
>  #if defined(TARGET_PPC64)
> -static void gen_set_cr6_from_fpscr(DisasContext *ctx)
> +static void gen_set_cr1_from_fpscr(DisasContext *ctx)
>  {
>      TCGv_i32 tmp = tcg_temp_new_i32();
>      tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
> @@ -8187,7 +8187,7 @@ static void gen_set_cr6_from_fpscr(DisasContext *ctx)
>      tcg_temp_free_i32(tmp);
>  }
>  #else
> -static void gen_set_cr6_from_fpscr(DisasContext *ctx)
> +static void gen_set_cr1_from_fpscr(DisasContext *ctx)
>  {
>      gen_op_mtcr(4, cpu_fpscr, 28);
>  }
> @@ -8207,7 +8207,7 @@ static void gen_##name(DisasContext *ctx)        \
>      rb = gen_fprp_ptr(rB(ctx->opcode));          \
>      gen_helper_##name(cpu_env, rd, ra, rb);      \
>      if (unlikely(Rc(ctx->opcode) != 0)) {        \
> -        gen_set_cr6_from_fpscr(ctx);             \
> +        gen_set_cr1_from_fpscr(ctx);             \
>      }                                            \
>      tcg_temp_free_ptr(rd);                       \
>      tcg_temp_free_ptr(ra);                       \
> @@ -8265,7 +8265,7 @@ static void gen_##name(DisasContext *ctx)             \
>      u32_2 = tcg_const_i32(u32f2(ctx->opcode));        \
>      gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
>      if (unlikely(Rc(ctx->opcode) != 0)) {             \
> -        gen_set_cr6_from_fpscr(ctx);                  \
> +        gen_set_cr1_from_fpscr(ctx);                  \
>      }                                                 \
>      tcg_temp_free_ptr(rt);                            \
>      tcg_temp_free_ptr(rb);                            \
> @@ -8289,7 +8289,7 @@ static void gen_##name(DisasContext *ctx)        \
>      i32 = tcg_const_i32(i32fld(ctx->opcode));    \
>      gen_helper_##name(cpu_env, rt, ra, rb, i32); \
>      if (unlikely(Rc(ctx->opcode) != 0)) {        \
> -        gen_set_cr6_from_fpscr(ctx);             \
> +        gen_set_cr1_from_fpscr(ctx);             \
>      }                                            \
>      tcg_temp_free_ptr(rt);                       \
>      tcg_temp_free_ptr(rb);                       \
> @@ -8310,7 +8310,7 @@ static void gen_##name(DisasContext *ctx)        \
>      rb = gen_fprp_ptr(rB(ctx->opcode));          \
>      gen_helper_##name(cpu_env, rt, rb);          \
>      if (unlikely(Rc(ctx->opcode) != 0)) {        \
> -        gen_set_cr6_from_fpscr(ctx);             \
> +        gen_set_cr1_from_fpscr(ctx);             \
>      }                                            \
>      tcg_temp_free_ptr(rt);                       \
>      tcg_temp_free_ptr(rb);                       \
> @@ -8331,7 +8331,7 @@ static void gen_##name(DisasContext *ctx)          \
>      i32 = tcg_const_i32(i32fld(ctx->opcode));      \
>      gen_helper_##name(cpu_env, rt, rs, i32);       \
>      if (unlikely(Rc(ctx->opcode) != 0)) {          \
> -        gen_set_cr6_from_fpscr(ctx);               \
> +        gen_set_cr1_from_fpscr(ctx);               \
>      }                                              \
>      tcg_temp_free_ptr(rt);                         \
>      tcg_temp_free_ptr(rs);                         \
> 

Reviewed-by: Tom Musta <tommusta@gmail.com>
Tested-by: Tom Musta <tommusta@gmail.com>

  reply	other threads:[~2014-09-03 19:41 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-28 17:14 [Qemu-devel] [RFT/RFH PATCH 00/16] PPC speedup patches for TCG Paolo Bonzini
2014-08-28 17:14 ` [Qemu-devel] [PATCH 01/17] ppc: do not look at the MMU index Paolo Bonzini
2014-08-28 17:14 ` [Qemu-devel] [PATCH 02/17] ppc: avoid excessive TLB flushing Paolo Bonzini
2014-08-28 17:30   ` Peter Maydell
2014-08-28 19:35     ` Paolo Bonzini
2014-09-05  6:00       ` David Gibson
2014-09-05  7:10   ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-09-05 12:11     ` Paolo Bonzini
2014-09-09 16:42       ` Paolo Bonzini
2014-09-09 20:51         ` Alexander Graf
2014-08-28 17:14 ` [Qemu-devel] [PATCH 03/17] ppc: fix monitor access to CR Paolo Bonzini
2014-09-03 18:21   ` Tom Musta
2014-09-05  7:10     ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 17:15 ` [Qemu-devel] [PATCH 04/17] ppc: use ARRAY_SIZE in gdbstub.c Paolo Bonzini
2014-09-03 18:21   ` Tom Musta
2014-08-28 17:15 ` [Qemu-devel] [PATCH 05/17] ppc: use CRF_* in fpu_helper.c Paolo Bonzini
2014-09-03 18:21   ` Tom Musta
2014-08-28 17:15 ` [Qemu-devel] [PATCH 06/17] ppc: use CRF_* in int_helper.c Paolo Bonzini
2014-09-03 18:28   ` Tom Musta
2014-09-05  7:12     ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 17:15 ` [Qemu-devel] [PATCH 07/17] ppc: fix result of DLMZB when no zero bytes are found Paolo Bonzini
2014-09-03 18:28   ` Tom Musta
2014-09-05  7:26     ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 17:15 ` [Qemu-devel] [PATCH 08/17] ppc: introduce helpers for mfocrf/mtocrf Paolo Bonzini
2014-09-03 18:28   ` Tom Musta
2014-08-28 17:15 ` [Qemu-devel] [PATCH 09/17] ppc: reorganize gen_compute_fprf Paolo Bonzini
2014-09-03 18:29   ` Tom Musta
2014-08-28 17:15 ` [Qemu-devel] [PATCH 10/17] ppc: introduce gen_op_mfcr/gen_op_mtcr Paolo Bonzini
2014-09-03 18:58   ` Tom Musta
2014-08-28 17:15 ` [Qemu-devel] [PATCH 11/17] ppc: rename gen_set_cr6_from_fpscr Paolo Bonzini
2014-09-03 19:41   ` Tom Musta [this message]
2014-09-05  7:27     ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 17:15 ` [Qemu-devel] [PATCH 12/17] ppc: use movcond for isel Paolo Bonzini
2014-08-29 18:30   ` Richard Henderson
2014-09-03 19:41   ` Tom Musta
2014-09-15 13:39     ` Paolo Bonzini
2014-08-28 17:15 ` [Qemu-devel] [PATCH 13/17] ppc: compute mask from BI using right shift Paolo Bonzini
2014-09-03 20:59   ` Tom Musta
2014-09-05  7:29     ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 17:15 ` [Qemu-devel] [PATCH 14/17] ppc: introduce ppc_get_crf and ppc_set_crf Paolo Bonzini
2014-09-04 18:26   ` Tom Musta
2014-08-28 17:15 ` [Qemu-devel] [PATCH 15/17] ppc: store CR registers in 32 1-bit registers Paolo Bonzini
2014-09-04 18:27   ` Tom Musta
2014-09-09 15:44     ` Paolo Bonzini
2014-09-09 16:41       ` Paolo Bonzini
2014-09-09 16:03     ` Richard Henderson
2014-09-09 16:26       ` Paolo Bonzini
2014-08-28 17:15 ` [Qemu-devel] [PATCH 16/17] ppc: inline ppc_get_crf/ppc_set_crf when clearer Paolo Bonzini
2014-08-28 17:15 ` [Qemu-devel] [PATCH 17/17] ppc: dump all 32 CR bits Paolo Bonzini
2014-08-28 18:05 ` [Qemu-devel] [RFT/RFH PATCH 00/16] PPC speedup patches for TCG Tom Musta

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