From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47056) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XPHeb-0001Xa-5k for qemu-devel@nongnu.org; Wed, 03 Sep 2014 16:59:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XPHeS-0005rS-4P for qemu-devel@nongnu.org; Wed, 03 Sep 2014 16:59:45 -0400 Message-ID: <54078127.8050108@gmail.com> Date: Wed, 03 Sep 2014 15:59:19 -0500 From: Tom Musta MIME-Version: 1.0 References: <1409246113-6519-1-git-send-email-pbonzini@redhat.com> <1409246113-6519-14-git-send-email-pbonzini@redhat.com> In-Reply-To: <1409246113-6519-14-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 13/17] ppc: compute mask from BI using right shift List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: dgibson@redhat.com, qemu-ppc@nongnu.org On 8/28/2014 12:15 PM, Paolo Bonzini wrote: > This will match the code we use in fpu_helper.c when we flip > CRF_* bit-endianness. > > Signed-off-by: Paolo Bonzini > --- > target-ppc/translate.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 48c7b66..4ce7af4 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -794,7 +794,7 @@ static void gen_isel(DisasContext *ctx) > TCGv_i32 t0; > TCGv t1, true_op, zero; > > - mask = 1 << (3 - (bi & 0x03)); > + mask = 0x08 >> (bi & 0x03); > t0 = tcg_temp_new_i32(); > tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask); > t1 = tcg_temp_new(); > @@ -3870,7 +3870,7 @@ static inline void gen_bcond(DisasContext *ctx, int type) > if ((bo & 0x10) == 0) { > /* Test CR */ > uint32_t bi = BI(ctx->opcode); > - uint32_t mask = 1 << (3 - (bi & 0x03)); > + uint32_t mask = 0x08 >> (bi & 0x03); > TCGv_i32 temp = tcg_temp_new_i32(); > > if (bo & 0x8) { > @@ -3952,7 +3952,7 @@ static void glue(gen_, name)(DisasContext *ctx) > else \ > tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ > tcg_op(t0, t0, t1); \ > - bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \ > + bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ > tcg_gen_andi_i32(t0, t0, bitmask); \ > tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ > tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ > Reviewed-by: Tom Musta Tested-by: Tom Musta