Re: [Qemu-devel] [PATCH 1/2] apb: add implementation of UltraSPARC IIi PCI TAS register

[Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>]

On 28/08/14 12:33, Artyom Tarasenko wrote:

> On Mon, Aug 25, 2014 at 7:58 PM, Mark Cave-Ayland
> <mark.cave-ayland@ilande.co.uk> wrote:
>> FreeBSD SPARC64 checks the value of this register on boot in order to calculate
>> the DVMA base address.
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>>   hw/pci-host/apb.c |   11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
>> index 60bd81e..3b7fb13 100644
>> --- a/hw/pci-host/apb.c
>> +++ b/hw/pci-host/apb.c
>> @@ -68,6 +68,11 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
>>   #define PBM_PCI_IMR_MASK    0x7fffffff
>>   #define PBM_PCI_IMR_ENABLED 0x80000000
>>
>> +/* PCI Target Address Space Register (see UltraSPARC IIi User's Manual
>> +   section 19.3.0.4) */
>> +#define PBM_PCI_TARGET_AS              0x2028
>> +#define PBM_PCI_TARGET_AS_CD_ENABLE    0x40
>> +
>>   #define POR          (1U << 31)
>>   #define SOFT_POR     (1U << 30)
>>   #define SOFT_XIR     (1U << 29)
>> @@ -731,6 +736,12 @@ static void pci_pbm_reset(DeviceState *d)
>>       s->irq_request = NO_IRQ_REQUEST;
>>       s->pci_irq_in = 0ULL;
>>
>> +    /* Set target address space register to base 0xc0000000, size 0x20000000
>> +       to match OpenBIOS virtual-dma properties */
>> +    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2)] = 0x0;
>> +    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2) + 1] =
>> +            PBM_PCI_TARGET_AS_CD_ENABLE;
>> +
>
> [nit-picking]
> Shouldn't it be other way around: set the register to POR state (0)
> here and set in OpenBIOS the desired values?
> Currently OpenBIOS is the only firmware, so it doesn't matter, but who knows...
> [/nit-picking]

Yes you could be right, at least it would make more sense to have 
OpenBIOS control the register so that we can guarantee that the value 
programmed matches the virtual-dma device tree properties. I'll go ahead 
and submit a pull request with just the PCI error register patch for the 
moment.


ATB,

Mark.