[Qemu-devel] [PATCH 0/2] apb: more PCI fixes

[Qemu-devel] [PATCH 0/2] apb: more PCI fixes

[Mark Cave-Ayland]

This patchset contains a couple of extra apb PCI fixes for bugs found whilst
trying to boot *BSDs on SPARC64.

With these patches qemu-system-sparc64 can now boot OpenBSD in -nographic
mode.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


Mark Cave-Ayland (2):
  apb: add implementation of UltraSPARC IIi PCI TAS register
  apb: implement PCI bus error interrupt map registers

 hw/pci-host/apb.c |   26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

-- 
1.7.10.4

[Qemu-devel] [PATCH 1/2] apb: add implementation of UltraSPARC IIi PCI TAS register

[Mark Cave-Ayland]

FreeBSD SPARC64 checks the value of this register on boot in order to calculate
the DVMA base address.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/pci-host/apb.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 60bd81e..3b7fb13 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -68,6 +68,11 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
 #define PBM_PCI_IMR_MASK    0x7fffffff
 #define PBM_PCI_IMR_ENABLED 0x80000000
 
+/* PCI Target Address Space Register (see UltraSPARC IIi User's Manual
+   section 19.3.0.4) */
+#define PBM_PCI_TARGET_AS              0x2028
+#define PBM_PCI_TARGET_AS_CD_ENABLE    0x40
+
 #define POR          (1U << 31)
 #define SOFT_POR     (1U << 30)
 #define SOFT_XIR     (1U << 29)
@@ -731,6 +736,12 @@ static void pci_pbm_reset(DeviceState *d)
     s->irq_request = NO_IRQ_REQUEST;
     s->pci_irq_in = 0ULL;
 
+    /* Set target address space register to base 0xc0000000, size 0x20000000
+       to match OpenBIOS virtual-dma properties */
+    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2)] = 0x0;
+    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2) + 1] =
+            PBM_PCI_TARGET_AS_CD_ENABLE;
+
     if (s->nr_resets++ == 0) {
         /* Power on reset */
         s->reset_control = POR;
-- 
1.7.10.4

[Qemu-devel] [PATCH 2/2] apb: implement PCI bus error interrupt map registers

[Mark Cave-Ayland]

Both OpenBSD and FreeBSD SPARC64 attempt to read the interrupt map from the
hardware and will fail if the correct ino isn't present.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/pci-host/apb.c |   15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 3b7fb13..d2c5c14 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -147,6 +147,7 @@ typedef struct APBState {
     IOMMUState iommu;
     uint32_t pci_control[16];
     uint32_t pci_irq_map[8];
+    uint32_t pci_err_irq_map[4];
     uint32_t obio_irq_map[32];
     qemu_irq *pbm_irqs;
     qemu_irq *ivec_irqs;
@@ -441,7 +442,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
             pbm_check_irqs(s);
         }
         break;
-    case 0x1000 ... 0x1080: /* OBIO interrupt control */
+    case 0x1000 ... 0x107f: /* OBIO interrupt control */
         if (addr & 4) {
             unsigned int ino = ((addr & 0xff) >> 3);
             s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
@@ -519,13 +520,20 @@ static uint64_t apb_config_readl (void *opaque,
             val = 0;
         }
         break;
-    case 0x1000 ... 0x1080: /* OBIO interrupt control */
+    case 0x1000 ... 0x107f: /* OBIO interrupt control */
         if (addr & 4) {
             val = s->obio_irq_map[(addr & 0xff) >> 3];
         } else {
             val = 0;
         }
         break;
+    case 0x1080 ... 0x108f: /* PCI bus error */
+        if (addr & 4) {
+            val = s->pci_err_irq_map[(addr & 0xf) >> 3];
+        } else {
+            val = 0;
+        }
+        break;
     case 0x2000 ... 0x202f: /* PCI control */
         val = s->pci_control[(addr & 0x3f) >> 2];
         break;
@@ -763,6 +771,9 @@ static int pci_pbm_init_device(SysBusDevice *dev)
     for (i = 0; i < 8; i++) {
         s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
     }
+    for (i = 0; i < 2; i++) {
+        s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
+    }
     for (i = 0; i < 32; i++) {
         s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
     }
-- 
1.7.10.4

Re: [Qemu-devel] [PATCH 2/2] apb: implement PCI bus error interrupt map registers

[Artyom Tarasenko]

On Mon, Aug 25, 2014 at 7:58 PM, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
> Both OpenBSD and FreeBSD SPARC64 attempt to read the interrupt map from the
> hardware and will fail if the correct ino isn't present.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>

> ---
>  hw/pci-host/apb.c |   15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 3b7fb13..d2c5c14 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -147,6 +147,7 @@ typedef struct APBState {
>      IOMMUState iommu;
>      uint32_t pci_control[16];
>      uint32_t pci_irq_map[8];
> +    uint32_t pci_err_irq_map[4];
>      uint32_t obio_irq_map[32];
>      qemu_irq *pbm_irqs;
>      qemu_irq *ivec_irqs;
> @@ -441,7 +442,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
>              pbm_check_irqs(s);
>          }
>          break;
> -    case 0x1000 ... 0x1080: /* OBIO interrupt control */
> +    case 0x1000 ... 0x107f: /* OBIO interrupt control */
>          if (addr & 4) {
>              unsigned int ino = ((addr & 0xff) >> 3);
>              s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK;
> @@ -519,13 +520,20 @@ static uint64_t apb_config_readl (void *opaque,
>              val = 0;
>          }
>          break;
> -    case 0x1000 ... 0x1080: /* OBIO interrupt control */
> +    case 0x1000 ... 0x107f: /* OBIO interrupt control */
>          if (addr & 4) {
>              val = s->obio_irq_map[(addr & 0xff) >> 3];
>          } else {
>              val = 0;
>          }
>          break;
> +    case 0x1080 ... 0x108f: /* PCI bus error */
> +        if (addr & 4) {
> +            val = s->pci_err_irq_map[(addr & 0xf) >> 3];
> +        } else {
> +            val = 0;
> +        }
> +        break;
>      case 0x2000 ... 0x202f: /* PCI control */
>          val = s->pci_control[(addr & 0x3f) >> 2];
>          break;
> @@ -763,6 +771,9 @@ static int pci_pbm_init_device(SysBusDevice *dev)
>      for (i = 0; i < 8; i++) {
>          s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
>      }
> +    for (i = 0; i < 2; i++) {
> +        s->pci_err_irq_map[i] = (0x1f << 6) | 0x30;
> +    }
>      for (i = 0; i < 32; i++) {
>          s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
>      }
> --
> 1.7.10.4
>
>



-- 
Regards,
Artyom Tarasenko

linux/sparc and solaris/sparc under qemu blog:
http://tyom.blogspot.com/search/label/qemu

Re: [Qemu-devel] [PATCH 1/2] apb: add implementation of UltraSPARC IIi PCI TAS register

[Artyom Tarasenko]

On Mon, Aug 25, 2014 at 7:58 PM, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
> FreeBSD SPARC64 checks the value of this register on boot in order to calculate
> the DVMA base address.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
>  hw/pci-host/apb.c |   11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 60bd81e..3b7fb13 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -68,6 +68,11 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
>  #define PBM_PCI_IMR_MASK    0x7fffffff
>  #define PBM_PCI_IMR_ENABLED 0x80000000
>
> +/* PCI Target Address Space Register (see UltraSPARC IIi User's Manual
> +   section 19.3.0.4) */
> +#define PBM_PCI_TARGET_AS              0x2028
> +#define PBM_PCI_TARGET_AS_CD_ENABLE    0x40
> +
>  #define POR          (1U << 31)
>  #define SOFT_POR     (1U << 30)
>  #define SOFT_XIR     (1U << 29)
> @@ -731,6 +736,12 @@ static void pci_pbm_reset(DeviceState *d)
>      s->irq_request = NO_IRQ_REQUEST;
>      s->pci_irq_in = 0ULL;
>
> +    /* Set target address space register to base 0xc0000000, size 0x20000000
> +       to match OpenBIOS virtual-dma properties */
> +    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2)] = 0x0;
> +    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2) + 1] =
> +            PBM_PCI_TARGET_AS_CD_ENABLE;
> +

[nit-picking]
Shouldn't it be other way around: set the register to POR state (0)
here and set in OpenBIOS the desired values?
Currently OpenBIOS is the only firmware, so it doesn't matter, but who knows...
[/nit-picking]

Artyom

>      if (s->nr_resets++ == 0) {
>          /* Power on reset */
>          s->reset_control = POR;
> --
> 1.7.10.4
>
>



-- 
Regards,
Artyom Tarasenko

linux/sparc and solaris/sparc under qemu blog:
http://tyom.blogspot.com/search/label/qemu

Re: [Qemu-devel] [PATCH 1/2] apb: add implementation of UltraSPARC IIi PCI TAS register

[Mark Cave-Ayland]

On 28/08/14 12:33, Artyom Tarasenko wrote:

> On Mon, Aug 25, 2014 at 7:58 PM, Mark Cave-Ayland
> <mark.cave-ayland@ilande.co.uk> wrote:
>> FreeBSD SPARC64 checks the value of this register on boot in order to calculate
>> the DVMA base address.
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>>   hw/pci-host/apb.c |   11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
>> index 60bd81e..3b7fb13 100644
>> --- a/hw/pci-host/apb.c
>> +++ b/hw/pci-host/apb.c
>> @@ -68,6 +68,11 @@ do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
>>   #define PBM_PCI_IMR_MASK    0x7fffffff
>>   #define PBM_PCI_IMR_ENABLED 0x80000000
>>
>> +/* PCI Target Address Space Register (see UltraSPARC IIi User's Manual
>> +   section 19.3.0.4) */
>> +#define PBM_PCI_TARGET_AS              0x2028
>> +#define PBM_PCI_TARGET_AS_CD_ENABLE    0x40
>> +
>>   #define POR          (1U << 31)
>>   #define SOFT_POR     (1U << 30)
>>   #define SOFT_XIR     (1U << 29)
>> @@ -731,6 +736,12 @@ static void pci_pbm_reset(DeviceState *d)
>>       s->irq_request = NO_IRQ_REQUEST;
>>       s->pci_irq_in = 0ULL;
>>
>> +    /* Set target address space register to base 0xc0000000, size 0x20000000
>> +       to match OpenBIOS virtual-dma properties */
>> +    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2)] = 0x0;
>> +    s->pci_control[((PBM_PCI_TARGET_AS & 0x3f) >> 2) + 1] =
>> +            PBM_PCI_TARGET_AS_CD_ENABLE;
>> +
>
> [nit-picking]
> Shouldn't it be other way around: set the register to POR state (0)
> here and set in OpenBIOS the desired values?
> Currently OpenBIOS is the only firmware, so it doesn't matter, but who knows...
> [/nit-picking]

Yes you could be right, at least it would make more sense to have 
OpenBIOS control the register so that we can guarantee that the value 
programmed matches the virtual-dma device tree properties. I'll go ahead 
and submit a pull request with just the PCI error register patch for the 
moment.


ATB,

Mark.