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Date: Tue, 09 Sep 2014 18:26:48 +0200
From: Paolo Bonzini <pbonzini@redhat.com>
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Subject: Re: [Qemu-devel] [PATCH 15/17] ppc: store CR registers in 32 1-bit
 registers
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To: Richard Henderson <rth@twiddle.net>, Tom Musta <tommusta@gmail.com>, qemu-devel@nongnu.org
Cc: dgibson@redhat.com, qemu-ppc@nongnu.org

Il 09/09/2014 18:03, Richard Henderson ha scritto:
> Note that since most hosts don't have nand, the combination
> 
>   nand x,y,z
>   and  x.x,1
> 
> would be better represented with
> 
>   and  x,y,z
>   xor  x,x,1

True (and even for crorc a,b,c you can change it to crandc a,c,b
followed by xor).  But this is quite a borderline case.  You'll find in
practice only "creqv a,a,a", which the optimizer can handle fine.

Paolo