Re: [Qemu-devel] [PATCH 15/17] ppc: store CR registers in 32 1-bit registers

[Paolo Bonzini <pbonzini@redhat.com>]

Il 09/09/2014 17:44, Paolo Bonzini ha scritto:
> Il 04/09/2014 20:27, Tom Musta ha scritto:
>>>> -    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
>>>> +    tcg_gen_trunc_tl_i32(cpu_cr[crf * 4 + CRF_SO], cpu_so);
>> This looks correct to me but is causing problems.  The above statement seems to get dropped in the generated asm ... at least on a PPC host:
>>
>> IN:
>> 0x00000000100005b4:  cmpw    cr3,r30,r29
>>
>> OUT: [size=160]
>> 0x6041ad30:  lwz     r14,-4(r27)
>> 0x6041ad34:  cmpwi   cr7,r14,0
>> 0x6041ad38:  bne-    cr7,0x6041adbc
>> 0x6041ad3c:  ld      r14,240(r27)   <<< r30
>> 0x6041ad40:  ld      r15,232(r27)   <<< r31
>> 0x6041ad44:  cmpw    cr7,r14,r15    <<< this is the TCG_COND_LTx code
>> 0x6041ad48:  li      r16,1
>> 0x6041ad4c:  li      r0,0
>> 0x6041ad50:  isel    r16,r16,r0,28
>> 0x6041ad54:  stw     r16,576(r27)   <<< store cpu_cr[LT]
>> 0x6041ad58:  cmpw    cr7,r14,r15
>> 0x6041ad5c:  li      r16,1
>> 0x6041ad60:  li      r0,0
>> 0x6041ad64:  isel    r16,r16,r0,29
>> 0x6041ad68:  stw     r16,580(r27)   <<< store cpu_cr[GT]
>> 0x6041ad6c:  cmplw   cr7,r14,r15
>> 0x6041ad70:  li      r14,1
>> 0x6041ad74:  li      r0,0
>> 0x6041ad78:  isel    r14,r14,r0,30
>> 0x6041ad7c:  stw     r14,584(r27)   <<< store cpu_cr[EQ]
>> 0x6041ad80:  .long 0x0
>> 0x6041ad84:  .long 0x0
> 
> If this is 32-bit, the problem is simply that the trunc is missing in
> gen_op_cmp32.  I still see a bunch of failures with the patches though,
> I'll look into them as I have time.

Nah, the failure was a bug in the new function I introduced to get all
32 CR bits as a uint32_t (as you suggested in the reply to patch 4).

Paolo