From: Alexander Graf <agraf@suse.de>
To: Pierre Mallard <mallard.pierre@gmail.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: tommusta@gmail.com
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs
Date: Wed, 10 Sep 2014 11:20:14 +0200 [thread overview]
Message-ID: <541017CE.1090704@suse.de> (raw)
In-Reply-To: <1410325413-3660-1-git-send-email-mallard.pierre@gmail.com>
On 10.09.14 07:03, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs
> which have the capabilities to have optional APU FPU.
>
> 1) Add floating point standard insns flag to 440x5 in case there is an apu fpu.
> 2) Define a new floating point insns flag for operation
> previously reserved to 64 bits proc (fcfid, fctid, fctidz)
> 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64
> restrictions
I've looked through the patches mostly from a stylistic point of view.
As for whether the changes are technically correct and fully adhere to
the specs, I haven't verified anything and would leave that part to Tom :).
Alex
next prev parent reply other threads:[~2014-09-10 9:20 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-10 5:03 [Qemu-devel] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs Pierre Mallard
2014-09-10 5:03 ` [Qemu-devel] [PATCH 1/3] target-ppc : Add floating point ability to 440x5 PPC CPU Pierre Mallard
2014-09-10 9:13 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-09-10 5:03 ` [Qemu-devel] [PATCH 2/3] target-ppc : Add PPC_FLOAT_64 flag to instructions type Pierre Mallard
2014-09-10 9:18 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-09-10 16:23 ` Tom Musta
2014-09-10 5:03 ` [Qemu-devel] [PATCH 3/3] target-ppc : Add PPC_FLOAT_64 type to fctid, fctidz and fcfid and remove their TARGET_PPC64 restriction Pierre Mallard
2014-09-10 9:19 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-09-10 16:44 ` Tom Musta
2014-09-10 9:20 ` Alexander Graf [this message]
2014-09-10 17:15 ` [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs Tom Musta
2014-09-10 18:02 ` Pierre Mallard
2014-09-10 22:43 ` Pierre Mallard
2014-09-11 12:30 ` Tom Musta
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