From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46784) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XRe4c-0007Hn-I9 for qemu-devel@nongnu.org; Wed, 10 Sep 2014 05:20:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XRe4U-00027l-Vh for qemu-devel@nongnu.org; Wed, 10 Sep 2014 05:20:22 -0400 Message-ID: <541017CE.1090704@suse.de> Date: Wed, 10 Sep 2014 11:20:14 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1410325413-3660-1-git-send-email-mallard.pierre@gmail.com> In-Reply-To: <1410325413-3660-1-git-send-email-mallard.pierre@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point instruction to 440x5 CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pierre Mallard , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: tommusta@gmail.com On 10.09.14 07:03, Pierre Mallard wrote: > This patch series enable floating point instruction in 440x5 CPUs > which have the capabilities to have optional APU FPU. > > 1) Add floating point standard insns flag to 440x5 in case there is an apu fpu. > 2) Define a new floating point insns flag for operation > previously reserved to 64 bits proc (fcfid, fctid, fctidz) > 3) Apply this new flag to fcfid, fctid, fctidz and move TARGET_PPC64 > restrictions I've looked through the patches mostly from a stylistic point of view. As for whether the changes are technically correct and fully adhere to the specs, I haven't verified anything and would leave that part to Tom :). Alex