From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XST6R-0002Fy-D8 for qemu-devel@nongnu.org; Fri, 12 Sep 2014 11:49:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XST6I-0006h3-95 for qemu-devel@nongnu.org; Fri, 12 Sep 2014 11:49:39 -0400 Received: from mail-qc0-x22c.google.com ([2607:f8b0:400d:c01::22c]:51749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XST6I-0006gz-40 for qemu-devel@nongnu.org; Fri, 12 Sep 2014 11:49:30 -0400 Received: by mail-qc0-f172.google.com with SMTP id i17so923680qcy.17 for ; Fri, 12 Sep 2014 08:49:28 -0700 (PDT) Sender: Richard Henderson Message-ID: <54131603.1070202@twiddle.net> Date: Fri, 12 Sep 2014 08:49:23 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1409762817-24029-1-git-send-email-rth@twiddle.net> <1409762817-24029-3-git-send-email-rth@twiddle.net> <5412FFC6.7040903@huawei.com> In-Reply-To: <5412FFC6.7040903@huawei.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] tcg-aarch64: Use 32-bit loads for qemu_ld_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Claudio Fontana , qemu-devel@nongnu.org On 09/12/2014 07:14 AM, Claudio Fontana wrote: >> > +++ b/tcg/tcg.h >> > @@ -194,7 +194,6 @@ typedef struct TCGPool { >> > typedef enum TCGType { >> > TCG_TYPE_I32, >> > TCG_TYPE_I64, >> > - TCG_TYPE_COUNT, /* number of different types */ >> > >> > /* An alias for the size of the host register. */ >> > #if TCG_TARGET_REG_BITS == 32 >> > @@ -218,6 +217,8 @@ typedef enum TCGType { >> > #endif >> > } TCGType; >> > >> > +#define TCG_TYPE_COUNT 2 >> > + > why this move from the enum to this standalone define? > Becuase having the 2 in the enum makes the compiler think we need 2 bits to store the enum instead of one. I should probably have pulled that out. r~