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Date: Fri, 12 Sep 2014 21:46:40 +0200
From: Alexander Graf <agraf@suse.de>
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 0/2] Enabling floating point
 instruction to 440x5 CPUs
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To: Pierre Mallard <mallard.pierre@gmail.com>, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: agraf@suze.de, tommusta@gmail.com



On 12.09.14 21:31, Pierre Mallard wrote:
> This patch series enable floating point instruction in 440x5 CPUs
> which have the capabilities to have optional APU FPU in double precision mode.
> 
> 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag
> 2) Create a new 440x5 implementing floating point instructions

Thanks, applied to ppc-next.


Alex