From: Paolo Bonzini <pbonzini@redhat.com>
To: Richard Henderson <rth@twiddle.net>,
Tom Musta <tommusta@gmail.com>,
qemu-devel@nongnu.org
Cc: agraf@suse.de
Subject: Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes
Date: Tue, 16 Sep 2014 20:27:26 +0200 [thread overview]
Message-ID: <5418810E.3080100@redhat.com> (raw)
In-Reply-To: <54187B3D.8000909@twiddle.net>
Il 16/09/2014 20:02, Richard Henderson ha scritto:
> While we could probably fix this for ppc (using addis), it's not nearly so
> easily fixable for arm -- without impacting performance anyway.
>
> Does 96k worth of TLBs really help that much? Are all 12 of them actually
> used? Can we use a more complex encoding scheme for the mmu_idx and use less?
In practice, only 3 to 7 are---hence my original attempt at using some
kind of FIFO caching:
user mode, translation enabled
kernel mode, paging disabled
kernel mode, paging enabled
supervisor mode, paging disabled
supervisor mode, paging enabled
Plus perhaps kernel and supervisor mode with only data paging enabled.
You could lump together the IR!=0, DR!=0 cases, and flush that one TLB
index if the IR/DR pair changes with respect to the last time. This
would use 6 indices.
Paolo
next prev parent reply other threads:[~2014-09-16 18:27 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-15 15:03 [Qemu-devel] [PATCH v2 00/14] TCG ppc speedups Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 01/14] ppc: do not look at the MMU index to detect PR/HV mode Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 02/14] softmmu: support up to 12 MMU modes Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes Paolo Bonzini
2014-09-16 17:20 ` Tom Musta
2014-09-16 18:02 ` Richard Henderson
2014-09-16 18:27 ` Paolo Bonzini [this message]
2014-09-16 18:41 ` Richard Henderson
2014-09-16 22:23 ` Richard Henderson
2014-09-17 6:22 ` Paolo Bonzini
2014-09-17 8:53 ` Paolo Bonzini
2014-09-17 15:33 ` Richard Henderson
2014-09-17 15:50 ` Paolo Bonzini
2014-09-17 15:55 ` Richard Henderson
2014-09-16 18:49 ` Peter Maydell
2014-09-16 22:13 ` Richard Henderson
2014-09-15 15:03 ` [Qemu-devel] [PATCH 04/14] ppc: introduce ppc_get_cr and ppc_set_cr Paolo Bonzini
2014-09-18 19:24 ` Tom Musta
2014-09-15 15:03 ` [Qemu-devel] [PATCH 05/14] ppc: use CRF_* in fpu_helper.c Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 06/14] ppc: introduce helpers for mfocrf/mtocrf Paolo Bonzini
2014-09-18 19:32 ` Tom Musta
2014-09-18 21:01 ` Richard Henderson
2014-09-15 15:03 ` [Qemu-devel] [PATCH 07/14] ppc: reorganize gen_compute_fprf Paolo Bonzini
2014-09-18 19:48 ` Tom Musta
2014-09-15 15:03 ` [Qemu-devel] [PATCH 08/14] ppc: introduce gen_op_mfcr/gen_op_mtcr Paolo Bonzini
2014-09-18 19:49 ` Tom Musta
2014-09-18 21:38 ` Richard Henderson
2014-09-19 13:31 ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 09/14] ppc: introduce ppc_get_crf and ppc_set_crf Paolo Bonzini
2014-09-18 19:51 ` Tom Musta
2014-09-19 14:52 ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 10/14] ppc: use movcond for isel Paolo Bonzini
2014-09-18 20:05 ` Tom Musta
2014-09-15 15:03 ` [Qemu-devel] [PATCH 11/14] ppc: store CR registers in 32 1-bit registers Paolo Bonzini
2014-09-18 20:25 ` Tom Musta
2014-09-19 13:53 ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 12/14] ppc: use movcond to implement evsel Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 13/14] ppc: inline ppc_set_crf when clearer Paolo Bonzini
2014-09-18 20:33 ` Tom Musta
2014-09-19 13:51 ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 14/14] ppc: dump all 32 CR bits Paolo Bonzini
2014-09-18 20:43 ` [Qemu-devel] [PATCH v2 00/14] TCG ppc speedups Tom Musta
2014-09-19 15:16 ` Paolo Bonzini
2014-11-03 11:56 ` Alexander Graf
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