From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XTxhb-00012I-Ji for qemu-devel@nongnu.org; Tue, 16 Sep 2014 14:42:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XTxhR-0002xj-EZ for qemu-devel@nongnu.org; Tue, 16 Sep 2014 14:42:11 -0400 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]:49231) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XTxhR-0002wJ-6y for qemu-devel@nongnu.org; Tue, 16 Sep 2014 14:42:01 -0400 Received: by mail-pd0-f177.google.com with SMTP id y10so341074pdj.8 for ; Tue, 16 Sep 2014 11:41:57 -0700 (PDT) Sender: Richard Henderson Message-ID: <5418846E.8070608@twiddle.net> Date: Tue, 16 Sep 2014 11:41:50 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> <1410793421-6453-4-git-send-email-pbonzini@redhat.com> <5418716A.9080508@gmail.com> <54187B3D.8000909@twiddle.net> <5418810E.3080100@redhat.com> In-Reply-To: <5418810E.3080100@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , Tom Musta , qemu-devel@nongnu.org Cc: agraf@suse.de On 09/16/2014 11:27 AM, Paolo Bonzini wrote: > Il 16/09/2014 20:02, Richard Henderson ha scritto: >> While we could probably fix this for ppc (using addis), it's not nearly so >> easily fixable for arm -- without impacting performance anyway. >> >> Does 96k worth of TLBs really help that much? Are all 12 of them actually >> used? Can we use a more complex encoding scheme for the mmu_idx and use less? > > In practice, only 3 to 7 are---hence my original attempt at using some > kind of FIFO caching: > > user mode, translation enabled > kernel mode, paging disabled > kernel mode, paging enabled > supervisor mode, paging disabled > supervisor mode, paging enabled > > Plus perhaps kernel and supervisor mode with only data paging enabled. > > You could lump together the IR!=0, DR!=0 cases, and flush that one TLB > index if the IR/DR pair changes with respect to the last time. This > would use 6 indices. I think I would prefer a solution that uses 6 indicies, as will not cause env to overflow 64k, and not require that any tcg backends be updated. r~