From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50504) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUAzT-00054n-Hg for qemu-devel@nongnu.org; Wed, 17 Sep 2014 04:53:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XUAzK-0002jI-GY for qemu-devel@nongnu.org; Wed, 17 Sep 2014 04:53:31 -0400 Sender: Paolo Bonzini Message-ID: <54194BF9.7010102@redhat.com> Date: Wed, 17 Sep 2014 10:53:13 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> <1410793421-6453-4-git-send-email-pbonzini@redhat.com> <5418716A.9080508@gmail.com> <54187B3D.8000909@twiddle.net> <5418810E.3080100@redhat.com> <5418846E.8070608@twiddle.net> <5418B877.8080308@twiddle.net> <1959651544.50247750.1410934939759.JavaMail.zimbra@redhat.com> In-Reply-To: <1959651544.50247750.1410934939759.JavaMail.zimbra@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: Peter Maydell , Tom Musta , qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org Il 17/09/2014 08:22, Paolo Bonzini ha scritto: > >> What if instead of having a "mmu_index" for the mmu arrays, we have a pointer >> to the "mmu context". This does imply an extra memory load on the fast path, >> but probably not an extra instruction. >> >> With this, we can suddenly afford to have a relatively large number of mmu >> contexts, with which we could implement address space numbers for relevant >> targets. >> >> It is, of course, a much larger change, but perhaps it's of larger benefit. > > Sounds good. I can give it a shot---in the meanwhile, since I forgot to > Cc qemu-ppc, Alex can you review/apply patch 1? Much simpler: let's cut the size of the TLB in half on affected targets. This does sacrifice some speed, but you still get about two thirds of the improvement (boot speed of a Debian installation ISO: 30s without patches, 24s with small TLB, 22s with large TLB) compared to the current TCG target. For 32-bit target and 32-bit host we can still use the full TLB size. The following can be easily squashed in patch 2: diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0ca6f0b..ed78884 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -69,8 +69,6 @@ typedef uint64_t target_ulong; #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) #if !defined(CONFIG_USER_ONLY) -#define CPU_TLB_BITS 8 -#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 @@ -80,6 +78,16 @@ typedef uint64_t target_ulong; #define CPU_TLB_ENTRY_BITS 5 #endif +/* All the TLBs together must be smaller than 64k on RISC machines */ +#if !defined(__i386__) && !defined(__x86_64__) && !defined(__aarch64__) \ + && !defined(__sparc__) && !defined(CONFIG_TCG_INTERPRETER) +#define CPU_TLB_BITS (NB_MMU_MODES < 8 ? 8 : 12 - CPU_TLB_ENTRY_BITS) +#else +#define CPU_TLB_BITS 8 +#endif + +#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) + typedef struct CPUTLBEntry { /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not Tom, can you test this on PPC? Paolo