From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50522) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUhRi-00081P-PB for qemu-devel@nongnu.org; Thu, 18 Sep 2014 15:32:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XUhRZ-0008M6-O1 for qemu-devel@nongnu.org; Thu, 18 Sep 2014 15:32:50 -0400 Received: from mail-ie0-x22f.google.com ([2607:f8b0:4001:c03::22f]:56894) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUhRZ-0008Lo-Gw for qemu-devel@nongnu.org; Thu, 18 Sep 2014 15:32:41 -0400 Received: by mail-ie0-f175.google.com with SMTP id lx4so2013131iec.20 for ; Thu, 18 Sep 2014 12:32:35 -0700 (PDT) Message-ID: <541B3348.5050306@gmail.com> Date: Thu, 18 Sep 2014 14:32:24 -0500 From: Tom Musta MIME-Version: 1.0 References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> <1410793421-6453-7-git-send-email-pbonzini@redhat.com> In-Reply-To: <1410793421-6453-7-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 06/14] ppc: introduce helpers for mfocrf/mtocrf List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: agraf@suse.de On 9/15/2014 10:03 AM, Paolo Bonzini wrote: > Signed-off-by: Paolo Bonzini > --- > v1->v2: used ARRAY_SIZE and ppc_get_cr > > target-ppc/helper.h | 3 +++ > target-ppc/int_helper.c | 17 +++++++++++++++++ > target-ppc/translate.c | 31 ++++--------------------------- > 3 files changed, 24 insertions(+), 27 deletions(-) > > diff --git a/target-ppc/helper.h b/target-ppc/helper.h > index 0cfdc8a..ee748a1 100644 > --- a/target-ppc/helper.h > +++ b/target-ppc/helper.h > @@ -59,6 +59,9 @@ DEF_HELPER_2(fpscr_setbit, void, env, i32) > DEF_HELPER_2(float64_to_float32, i32, env, i64) > DEF_HELPER_2(float32_to_float64, i64, env, i32) > > +DEF_HELPER_1(mfocrf, tl, env) > +DEF_HELPER_3(mtocrf, void, env, tl, i32) > + > DEF_HELPER_4(fcmpo, void, env, i64, i64, i32) > DEF_HELPER_4(fcmpu, void, env, i64, i64, i32) > > diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c > index 83c1ad0..54e8998 100644 > --- a/target-ppc/int_helper.c > +++ b/target-ppc/int_helper.c > @@ -289,6 +289,23 @@ target_ulong helper_popcntw(target_ulong val) > } > #endif > > +void helper_mtocrf(CPUPPCState *env, target_ulong cr, uint32_t mask) > +{ > + int i; > + for (i = ARRAY_SIZE(env->crf); --i >= 0; ) { > + if (mask & 1) { > + env->crf[i] = cr & 0x0F; > + } > + cr >>= 4; > + mask >>= 1; > + } > +} > + > +target_ulong helper_mfocrf(CPUPPCState *env) > +{ > + return ppc_get_cr(env); > +} > + > /*****************************************************************************/ > /* PowerPC 601 specific instructions (POWER bridge) */ > target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2) > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 2c9d8aa..c28bddf 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -4173,24 +4173,7 @@ static void gen_mfcr(DisasContext *ctx) > cpu_gpr[rD(ctx->opcode)], crn * 4); > } > } else { > - TCGv_i32 t0 = tcg_temp_new_i32(); > - tcg_gen_mov_i32(t0, cpu_crf[0]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[1]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[2]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[3]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[4]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[5]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[6]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[7]); > - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); > - tcg_temp_free_i32(t0); > + gen_helper_mfocrf(cpu_gpr[rD(ctx->opcode)], cpu_env); > } > } > > @@ -4285,15 +4268,9 @@ static void gen_mtcrf(DisasContext *ctx) > tcg_temp_free_i32(temp); > } > } else { > - TCGv_i32 temp = tcg_temp_new_i32(); > - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); > - for (crn = 0 ; crn < 8 ; crn++) { > - if (crm & (1 << crn)) { > - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); > - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); > - } > - } > - tcg_temp_free_i32(temp); > + TCGv_i32 t0 = tcg_const_i32(crm); > + gen_helper_mtocrf(cpu_env, cpu_gpr[rS(ctx->opcode)], t0); > + tcg_temp_free_i32(t0); > } > } > > Reviewed-by: Tom Musta Tested-by: Tom Musta