From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42042) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUipM-0005ML-JL for qemu-devel@nongnu.org; Thu, 18 Sep 2014 17:01:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XUipD-00069i-I3 for qemu-devel@nongnu.org; Thu, 18 Sep 2014 17:01:20 -0400 Received: from mail-qc0-x231.google.com ([2607:f8b0:400d:c01::231]:60174) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XUipD-000692-Dj for qemu-devel@nongnu.org; Thu, 18 Sep 2014 17:01:11 -0400 Received: by mail-qc0-f177.google.com with SMTP id o8so2110255qcw.36 for ; Thu, 18 Sep 2014 14:01:05 -0700 (PDT) Sender: Richard Henderson Message-ID: <541B480D.7030904@twiddle.net> Date: Thu, 18 Sep 2014 14:01:01 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> <1410793421-6453-7-git-send-email-pbonzini@redhat.com> In-Reply-To: <1410793421-6453-7-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 06/14] ppc: introduce helpers for mfocrf/mtocrf List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: tommusta@gmail.com, agraf@suse.de On 09/15/2014 08:03 AM, Paolo Bonzini wrote: > @@ -4173,24 +4173,7 @@ static void gen_mfcr(DisasContext *ctx) > cpu_gpr[rD(ctx->opcode)], crn * 4); > } > } else { > - TCGv_i32 t0 = tcg_temp_new_i32(); > - tcg_gen_mov_i32(t0, cpu_crf[0]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[1]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[2]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[3]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[4]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[5]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[6]); > - tcg_gen_shli_i32(t0, t0, 4); > - tcg_gen_or_i32(t0, t0, cpu_crf[7]); > - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); > - tcg_temp_free_i32(t0); > + gen_helper_mfocrf(cpu_gpr[rD(ctx->opcode)], cpu_env); I don't like this helper name, because it isn't mfocrf. We handled the "one" case above. This is the old-style "mfcr", i.e. move from all cr. > @@ -4285,15 +4268,9 @@ static void gen_mtcrf(DisasContext *ctx) > tcg_temp_free_i32(temp); > } > } else { > - TCGv_i32 temp = tcg_temp_new_i32(); > - tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); > - for (crn = 0 ; crn < 8 ; crn++) { > - if (crm & (1 << crn)) { > - tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); > - tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); > - } > - } > - tcg_temp_free_i32(temp); > + TCGv_i32 t0 = tcg_const_i32(crm); > + gen_helper_mtocrf(cpu_env, cpu_gpr[rS(ctx->opcode)], t0); > + tcg_temp_free_i32(t0); Similarly. r~