* [Qemu-devel] [PATCH v3 1/4] target-openrisc: New machine with IDE support
2014-10-05 11:01 [Qemu-devel] [PATCH v3 0/4] target-openrisc: Machine improvements take three Valentin Manea
@ 2014-10-05 11:03 ` Valentin Manea
2014-10-05 12:04 ` Jia Liu
2014-10-05 11:05 ` [Qemu-devel] [PATCH v3 2/4] hw/display: Add OpenCores FB device support Valentin Manea
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Valentin Manea @ 2014-10-05 11:03 UTC (permalink / raw)
To: qemu-devel@nongnu.org; +Cc: Jia Liu, Stefan Hajnoczi
Create new OpenRISC machine(asim) with default IDE support. It will
incude more peripherals in order to run a fully fledged Linux computer.
Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
---
default-configs/or32-softmmu.mak | 3 +
hw/openrisc/Makefile.objs | 1 +
hw/openrisc/openrisc_asim.c | 202 +++++++++++++++++++++++++++++++++++++++
3 files changed, 206 insertions(+)
create mode 100644 hw/openrisc/openrisc_asim.c
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
index cce4746..c3ff078 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -2,3 +2,6 @@
CONFIG_SERIAL=y
CONFIG_OPENCORES_ETH=y
+CONFIG_IDE_CORE=y
+CONFIG_IDE_QDEV=y
+CONFIG_IDE_MMIO=y
diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
index 61246b1..f266f5d 100644
--- a/hw/openrisc/Makefile.objs
+++ b/hw/openrisc/Makefile.objs
@@ -1,2 +1,3 @@
obj-y = pic_cpu.o cputimer.o
obj-y += openrisc_sim.o
+obj-y += openrisc_asim.o
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
new file mode 100644
index 0000000..80aa5ed
--- /dev/null
+++ b/hw/openrisc/openrisc_asim.c
@@ -0,0 +1,202 @@
+/*
+ * OpenRISC simulator with more peripherals
+ *
+ * Copyright (c) 2011-2014 Jia Liu <proljc@gmail.com>
+ * Feng Gao <gf91597@gmail.com>
+ * Valentin Manea <valentin.manea@gmail.com>
+ *
+ * This OpenRISC machine supports more hardware - same configuration as the
+ * jor1k(http://s-macke.github.io/jor1k). Currently the default Linux branch
+ * does not have all the support for this machine so the jor1k Linux kernel is
+ * needed for more advanced usecases: X support, compiling etc. You can download
+ * a precompiled image here http://mrs.ro/dl/or1k/vmlinux or compile it using
+ * the instructions at https://github.com/s-macke/jor1k/wiki
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/hw.h"
+#include "hw/boards.h"
+#include "elf.h"
+#include "hw/char/serial.h"
+#include "net/net.h"
+#include "hw/loader.h"
+#include "hw/ide.h"
+#include "exec/address-spaces.h"
+#include "sysemu/sysemu.h"
+#include "hw/sysbus.h"
+#include "sysemu/blockdev.h"
+#include "sysemu/qtest.h"
+
+#define KERNEL_LOAD_ADDR 0x100
+
+enum {
+ OR_UART0,
+ OR_IDE,
+ OR_OPENETH
+};
+
+static hwaddr mem_map[] = {
+ [OR_UART0] = 0x90000000,
+ [OR_IDE] = 0x9e000000,
+ [OR_OPENETH] = 0x92000000,
+};
+
+
+static void main_cpu_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void openrisc_sim_ide_init(MemoryRegion *address_space,
+ hwaddr base,
+ hwaddr descriptors,
+ qemu_irq irq)
+{
+ DeviceState *dev;
+ SysBusDevice *busdev;
+ DriveInfo *dinfo;
+
+
+ dinfo = drive_get(IF_IDE, 0, 0);
+ if (!dinfo) {
+ return;
+ }
+ dev = qdev_create(NULL, "mmio-ide");
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(busdev, 0, irq);
+ qdev_prop_set_uint32(dev, "shift", 2);
+ qdev_init_nofail(dev);
+ memory_region_add_subregion(address_space, base,
+ sysbus_mmio_get_region(busdev, 0));
+ memory_region_add_subregion(address_space, descriptors,
+ sysbus_mmio_get_region(busdev, 1));
+ mmio_ide_init_drives(dev, dinfo, NULL);
+}
+
+static void openrisc_sim_net_init(MemoryRegion *address_space,
+ hwaddr base,
+ hwaddr descriptors,
+ qemu_irq irq, NICInfo *nd)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+
+ dev = qdev_create(NULL, "open_eth");
+ qdev_set_nic_properties(dev, nd);
+ qdev_init_nofail(dev);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_connect_irq(s, 0, irq);
+ memory_region_add_subregion(address_space, base,
+ sysbus_mmio_get_region(s, 0));
+ memory_region_add_subregion(address_space, descriptors,
+ sysbus_mmio_get_region(s, 1));
+}
+
+static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ OpenRISCCPU *cpu)
+{
+ long kernel_size;
+ uint64_t elf_entry;
+ hwaddr entry;
+
+ if (kernel_filename && !qtest_enabled()) {
+ kernel_size = load_elf(kernel_filename, NULL, NULL,
+ &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
+ entry = elf_entry;
+ if (kernel_size < 0) {
+ kernel_size = load_uimage(kernel_filename,
+ &entry, NULL, NULL);
+ }
+ if (kernel_size < 0) {
+ kernel_size = load_image_targphys(kernel_filename,
+ KERNEL_LOAD_ADDR,
+ ram_size - KERNEL_LOAD_ADDR);
+ entry = KERNEL_LOAD_ADDR;
+ }
+
+ if (kernel_size < 0) {
+ fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",
+ kernel_filename);
+ exit(1);
+ }
+ cpu->env.pc = entry;
+ }
+}
+
+static void openrisc_sim_init(MachineState *machine)
+{
+ ram_addr_t ram_size = machine->ram_size;
+ const char *cpu_model = machine->cpu_model;
+ const char *kernel_filename = machine->kernel_filename;
+ OpenRISCCPU *cpu = NULL;
+ MemoryRegion *ram;
+ int n;
+
+ if (!cpu_model) {
+ cpu_model = "or1200";
+ }
+
+ for (n = 0; n < smp_cpus; n++) {
+ cpu = cpu_openrisc_init(cpu_model);
+ if (cpu == NULL) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+ qemu_register_reset(main_cpu_reset, cpu);
+ main_cpu_reset(cpu);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_abort);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ cpu_openrisc_pic_init(cpu);
+ cpu_openrisc_clock_init(cpu);
+
+ serial_mm_init(get_system_memory(), mem_map[OR_UART0], 0, cpu->env.irq[2],
+ 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
+
+ if (nd_table[0].used) {
+ openrisc_sim_net_init(get_system_memory(), mem_map[OR_OPENETH],
+ mem_map[OR_OPENETH] + 0x400, cpu->env.irq[4],
+ nd_table);
+ }
+
+ /* Platform ATA device */
+ openrisc_sim_ide_init(get_system_memory(), mem_map[OR_IDE],
+ mem_map[OR_IDE] + 0x100, cpu->env.irq[15]);
+
+
+ cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
+}
+
+static QEMUMachine openrisc_sim_machine = {
+ .name = "asim",
+ .desc = "or32 simulation",
+ .init = openrisc_sim_init,
+ .max_cpus = 1,
+};
+
+static void openrisc_sim_machine_init(void)
+{
+ qemu_register_machine(&openrisc_sim_machine);
+}
+
+machine_init(openrisc_sim_machine_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v3 1/4] target-openrisc: New machine with IDE support
2014-10-05 11:03 ` [Qemu-devel] [PATCH v3 1/4] target-openrisc: New machine with IDE support Valentin Manea
@ 2014-10-05 12:04 ` Jia Liu
0 siblings, 0 replies; 9+ messages in thread
From: Jia Liu @ 2014-10-05 12:04 UTC (permalink / raw)
To: Valentin Manea; +Cc: qemu-devel@nongnu.org, Stefan Hajnoczi
Hi Valentin,
On Sun, Oct 5, 2014 at 7:03 PM, Valentin Manea <valentin.manea@gmail.com> wrote:
> Create new OpenRISC machine(asim) with default IDE support. It will
> incude more peripherals in order to run a fully fledged Linux computer.
>
> Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
> ---
> default-configs/or32-softmmu.mak | 3 +
> hw/openrisc/Makefile.objs | 1 +
> hw/openrisc/openrisc_asim.c | 202 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 206 insertions(+)
> create mode 100644 hw/openrisc/openrisc_asim.c
>
> diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
> index cce4746..c3ff078 100644
> --- a/default-configs/or32-softmmu.mak
> +++ b/default-configs/or32-softmmu.mak
> @@ -2,3 +2,6 @@
>
> CONFIG_SERIAL=y
> CONFIG_OPENCORES_ETH=y
> +CONFIG_IDE_CORE=y
> +CONFIG_IDE_QDEV=y
> +CONFIG_IDE_MMIO=y
> diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
> index 61246b1..f266f5d 100644
> --- a/hw/openrisc/Makefile.objs
> +++ b/hw/openrisc/Makefile.objs
> @@ -1,2 +1,3 @@
> obj-y = pic_cpu.o cputimer.o
> obj-y += openrisc_sim.o
> +obj-y += openrisc_asim.o
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> new file mode 100644
> index 0000000..80aa5ed
> --- /dev/null
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -0,0 +1,202 @@
> +/*
> + * OpenRISC simulator with more peripherals
> + *
> + * Copyright (c) 2011-2014 Jia Liu <proljc@gmail.com>
> + * Feng Gao <gf91597@gmail.com>
> + * Valentin Manea <valentin.manea@gmail.com>
> + *
> + * This OpenRISC machine supports more hardware - same configuration as the
> + * jor1k(http://s-macke.github.io/jor1k). Currently the default Linux branch
> + * does not have all the support for this machine so the jor1k Linux kernel is
> + * needed for more advanced usecases: X support, compiling etc. You can download
> + * a precompiled image here http://mrs.ro/dl/or1k/vmlinux or compile it using
> + * the instructions at https://github.com/s-macke/jor1k/wiki
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/hw.h"
> +#include "hw/boards.h"
> +#include "elf.h"
> +#include "hw/char/serial.h"
> +#include "net/net.h"
> +#include "hw/loader.h"
> +#include "hw/ide.h"
> +#include "exec/address-spaces.h"
> +#include "sysemu/sysemu.h"
> +#include "hw/sysbus.h"
> +#include "sysemu/blockdev.h"
> +#include "sysemu/qtest.h"
> +
> +#define KERNEL_LOAD_ADDR 0x100
> +
> +enum {
> + OR_UART0,
> + OR_IDE,
> + OR_OPENETH
> +};
> +
> +static hwaddr mem_map[] = {
> + [OR_UART0] = 0x90000000,
> + [OR_IDE] = 0x9e000000,
> + [OR_OPENETH] = 0x92000000,
> +};
> +
> +
> +static void main_cpu_reset(void *opaque)
> +{
> + OpenRISCCPU *cpu = opaque;
> +
> + cpu_reset(CPU(cpu));
> +}
> +
> +static void openrisc_sim_ide_init(MemoryRegion *address_space,
> + hwaddr base,
> + hwaddr descriptors,
> + qemu_irq irq)
> +{
> + DeviceState *dev;
> + SysBusDevice *busdev;
> + DriveInfo *dinfo;
> +
> +
> + dinfo = drive_get(IF_IDE, 0, 0);
> + if (!dinfo) {
> + return;
> + }
> + dev = qdev_create(NULL, "mmio-ide");
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_connect_irq(busdev, 0, irq);
> + qdev_prop_set_uint32(dev, "shift", 2);
> + qdev_init_nofail(dev);
> + memory_region_add_subregion(address_space, base,
> + sysbus_mmio_get_region(busdev, 0));
> + memory_region_add_subregion(address_space, descriptors,
> + sysbus_mmio_get_region(busdev, 1));
> + mmio_ide_init_drives(dev, dinfo, NULL);
> +}
> +
> +static void openrisc_sim_net_init(MemoryRegion *address_space,
> + hwaddr base,
> + hwaddr descriptors,
> + qemu_irq irq, NICInfo *nd)
> +{
> + DeviceState *dev;
> + SysBusDevice *s;
> +
> + dev = qdev_create(NULL, "open_eth");
> + qdev_set_nic_properties(dev, nd);
> + qdev_init_nofail(dev);
> +
> + s = SYS_BUS_DEVICE(dev);
> + sysbus_connect_irq(s, 0, irq);
> + memory_region_add_subregion(address_space, base,
> + sysbus_mmio_get_region(s, 0));
> + memory_region_add_subregion(address_space, descriptors,
> + sysbus_mmio_get_region(s, 1));
> +}
> +
> +static void cpu_openrisc_load_kernel(ram_addr_t ram_size,
> + const char *kernel_filename,
> + OpenRISCCPU *cpu)
> +{
> + long kernel_size;
> + uint64_t elf_entry;
> + hwaddr entry;
> +
> + if (kernel_filename && !qtest_enabled()) {
> + kernel_size = load_elf(kernel_filename, NULL, NULL,
> + &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
> + entry = elf_entry;
> + if (kernel_size < 0) {
> + kernel_size = load_uimage(kernel_filename,
> + &entry, NULL, NULL);
> + }
> + if (kernel_size < 0) {
> + kernel_size = load_image_targphys(kernel_filename,
> + KERNEL_LOAD_ADDR,
> + ram_size - KERNEL_LOAD_ADDR);
> + entry = KERNEL_LOAD_ADDR;
> + }
> +
> + if (kernel_size < 0) {
> + fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",
> + kernel_filename);
> + exit(1);
> + }
> + cpu->env.pc = entry;
> + }
> +}
> +
> +static void openrisc_sim_init(MachineState *machine)
> +{
> + ram_addr_t ram_size = machine->ram_size;
> + const char *cpu_model = machine->cpu_model;
> + const char *kernel_filename = machine->kernel_filename;
> + OpenRISCCPU *cpu = NULL;
> + MemoryRegion *ram;
> + int n;
> +
> + if (!cpu_model) {
> + cpu_model = "or1200";
> + }
> +
> + for (n = 0; n < smp_cpus; n++) {
> + cpu = cpu_openrisc_init(cpu_model);
> + if (cpu == NULL) {
> + fprintf(stderr, "Unable to find CPU definition!\n");
> + exit(1);
> + }
> + qemu_register_reset(main_cpu_reset, cpu);
> + main_cpu_reset(cpu);
> + }
> +
> + ram = g_malloc(sizeof(*ram));
> + memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_abort);
> + vmstate_register_ram_global(ram);
> + memory_region_add_subregion(get_system_memory(), 0, ram);
> +
> + cpu_openrisc_pic_init(cpu);
> + cpu_openrisc_clock_init(cpu);
> +
> + serial_mm_init(get_system_memory(), mem_map[OR_UART0], 0, cpu->env.irq[2],
> + 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
> +
> + if (nd_table[0].used) {
> + openrisc_sim_net_init(get_system_memory(), mem_map[OR_OPENETH],
> + mem_map[OR_OPENETH] + 0x400, cpu->env.irq[4],
> + nd_table);
> + }
> +
> + /* Platform ATA device */
> + openrisc_sim_ide_init(get_system_memory(), mem_map[OR_IDE],
> + mem_map[OR_IDE] + 0x100, cpu->env.irq[15]);
> +
> +
> + cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> +}
> +
> +static QEMUMachine openrisc_sim_machine = {
> + .name = "asim",
> + .desc = "or32 simulation",
> + .init = openrisc_sim_init,
> + .max_cpus = 1,
> +};
> +
> +static void openrisc_sim_machine_init(void)
> +{
> + qemu_register_machine(&openrisc_sim_machine);
> +}
> +
> +machine_init(openrisc_sim_machine_init);
> --
> 1.9.1
>
>
Thank you for this new machine.
Reviewed-by: Jia Liu <proljc@gmail.com>
Regards,
Jia
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 2/4] hw/display: Add OpenCores FB device support
2014-10-05 11:01 [Qemu-devel] [PATCH v3 0/4] target-openrisc: Machine improvements take three Valentin Manea
2014-10-05 11:03 ` [Qemu-devel] [PATCH v3 1/4] target-openrisc: New machine with IDE support Valentin Manea
@ 2014-10-05 11:05 ` Valentin Manea
2014-10-05 12:07 ` Jia Liu
2014-10-05 11:06 ` [Qemu-devel] [PATCH v3 3/4] hw/input: Add OpenCores keyboard " Valentin Manea
2014-10-05 11:07 ` [Qemu-devel] [PATCH v3 4/4] hw/input: Add LPC32XX touchscreen device Valentin Manea
3 siblings, 1 reply; 9+ messages in thread
From: Valentin Manea @ 2014-10-05 11:05 UTC (permalink / raw)
To: qemu-devel@nongnu.org; +Cc: Jia Liu, Stefan Hajnoczi
>From edfd91e325a8c1806140c7468e187781d0b20ea9 Mon Sep 17 00:00:00 2001
From: Valentin Manea <valentin.manea@gmail.com>
Date: Sun, 21 Sep 2014 10:57:55 +0300
Subject: [PATCH 2/4] target-openrisc: Add OpenCores FB device support
Add support for the OpenCores Framebuffer device and enable it by
default in the OpenRISC asim machine.
The OpenCores display device is a simple open source framebuffer device
created http://opencores.org/project,vgafb
Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
---
default-configs/or32-softmmu.mak | 2 +
hw/display/Makefile.objs | 1 +
hw/display/ocfb.c | 315 ++++++++++++++++++++++++++++++++++++++
hw/display/ocfb.c.old | 321 +++++++++++++++++++++++++++++++++++++++
hw/openrisc/openrisc_asim.c | 8 +-
5 files changed, 646 insertions(+), 1 deletion(-)
create mode 100644 hw/display/ocfb.c
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
index c3ff078..036f591 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -5,3 +5,5 @@ CONFIG_OPENCORES_ETH=y
CONFIG_IDE_CORE=y
CONFIG_IDE_QDEV=y
CONFIG_IDE_MMIO=y
+CONFIG_FRAMEBUFFER=y
+CONFIG_OPENCORESFB=y
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 7ed76a9..4a755e6 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -33,3 +33,4 @@ obj-$(CONFIG_CG3) += cg3.o
obj-$(CONFIG_VGA) += vga.o
common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
+common-obj-$(CONFIG_OPENCORESFB) += ocfb.o
diff --git a/hw/display/ocfb.c b/hw/display/ocfb.c
new file mode 100644
index 0000000..fb2b7df
--- /dev/null
+++ b/hw/display/ocfb.c
@@ -0,0 +1,315 @@
+/*
+ * OpenCores framebuffer device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
+ * Based on Arm PrimeCell PL110 Color LCD Controller by Paul Brook
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/display/framebuffer.h"
+#include "ui/console.h"
+
+/* VGA defines */
+#define VGA_CTRL 0x000
+#define VGA_STAT 0x004
+#define VGA_HTIM 0x008
+#define VGA_VTIM 0x00c
+#define VGA_HVLEN 0x010
+#define VGA_VBARA 0x014
+#define VGA_PALETTE 0x800
+
+#define VGA_CTRL_VEN 0x00000001 /* Video Enable */
+#define VGA_CTRL_HIE 0x00000002 /* HSync Interrupt Enable */
+#define VGA_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/
+#define VGA_CTRL_CD8 0x00000000 /* Color Depth 8 */
+#define VGA_CTRL_CD16 0x00000200 /* Color Depth 16 */
+#define VGA_CTRL_CD24 0x00000400 /* Color Depth 24 */
+#define VGA_CTRL_CD32 0x00000600 /* Color Depth 32 */
+#define VGA_CTRL_CD 0x00000E00 /* Color Depth Mask */
+#define VGA_CTRL_VBL1 0x00000000 /* Burst Length 1 */
+#define VGA_CTRL_VBL2 0x00000080 /* Burst Length 2 */
+#define VGA_CTRL_VBL4 0x00000100 /* Burst Length 4 */
+#define VGA_CTRL_VBL8 0x00000180 /* Burst Length 8 */
+
+#define PALETTE_SIZE 256
+
+#define TYPE_OCFB "ocfb"
+#define OCFB(obj) OBJECT_CHECK(OCFBState, (obj), TYPE_OCFB)
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) \
+ do { printf("ocfb: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+typedef struct OCFBState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ QemuConsole *con;
+ /* RAM fragment containing framebuffer */
+ MemoryRegionSection mem_section;
+ uint32_t cr;
+ hwaddr fb;
+ uint32_t fb_size;
+ uint32_t cols;
+ uint32_t rows;
+ uint32_t bpp;
+ uint32_t invalidate;
+ qemu_irq irq;
+} OCFBState;
+
+static int vmstate_ocfb_post_load(void *opaque, int version_id);
+
+static const VMStateDescription vmstate_ocfb = {
+ .name = "ocfb",
+ .version_id = 2,
+ .minimum_version_id = 1,
+ .post_load = vmstate_ocfb_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(cr, OCFBState),
+ VMSTATE_UINT32(fb_size, OCFBState),
+ VMSTATE_UINT64(fb, OCFBState),
+ VMSTATE_UINT32(cols, OCFBState),
+ VMSTATE_UINT32(rows, OCFBState),
+ VMSTATE_UINT32(bpp, OCFBState),
+ VMSTATE_UINT32(invalidate, OCFBState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static int ocfb_enabled(OCFBState *s)
+{
+ return s->cr & VGA_CTRL_VEN;
+}
+
+static void ocfb_update_display(void *opaque)
+{
+ OCFBState *s = (OCFBState *)opaque;
+
+ if (!ocfb_enabled(s)) {
+ return;
+ }
+
+ memory_region_sync_dirty_bitmap(s->mem_section.mr);
+
+ int dirty = memory_region_get_dirty(s->mem_section.mr,
+ s->mem_section.offset_within_region, s->fb_size,
+ DIRTY_MEMORY_VGA);
+
+ if (dirty || s->invalidate) {
+ dpy_gfx_update(s->con, 0, 0, s->cols, s->rows);
+ }
+ s->invalidate = 0;
+ memory_region_reset_dirty(s->mem_section.mr,
+ s->mem_section.offset_within_region, s->fb_size,
+ DIRTY_MEMORY_VGA);
+}
+
+static void ocfb_invalidate_display(void *opaque)
+{
+ OCFBState *s = (OCFBState *)opaque;
+ s->invalidate = 1;
+}
+
+static void ocfb_ref_fb(OCFBState *s, hwaddr base, uint64_t src_len)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(s);
+
+ memory_region_unref(s->mem_section.mr);
+ s->mem_section = memory_region_find(sysbus_address_space(sbd), base,
+ src_len);
+ assert(s->mem_section.mr);
+ assert(s->mem_section.offset_within_address_space == base);
+
+ if (int128_get64(s->mem_section.size) != src_len ||
+ !memory_region_is_ram(s->mem_section.mr)) {
+ hw_error("Invalid framebuffer address!\n");
+ }
+}
+
+static uint64_t ocfb_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ DPRINTF("read at 0x%08X\n", (unsigned int)offset);
+ return 0;
+}
+
+
+static void ocfb_enable_console(OCFBState *s)
+{
+ DisplaySurface *surface;
+ if (!s->rows || !s->cols || !s->bpp) {
+ return;
+ }
+ if (!s->fb) {
+ return;
+ }
+ int stride = (s->cols * s->bpp) / 8;
+ s->fb_size = stride * s->rows;
+
+ ocfb_ref_fb(s, s->fb, s->fb_size);
+
+ pixman_format_code_t format = qemu_default_pixman_format(s->bpp, false);
+ /* console.c supported depth -> buffer can be used directly */
+ surface = qemu_create_displaysurface_guestmem(s->cols, s->rows, format,
+ 0, s->fb);
+ dpy_gfx_replace_surface(s->con, surface);
+}
+
+static inline void ocfb_read_htim(OCFBState *s, uint32_t val)
+{
+ /* uint32_t hsync_len = ((val >> 24) & 0xF) + 1;
+ uint32_t right_margin = ((val >> 16) & 0xF) + 1;*/
+ uint32_t xres = (val & 0xFFFF) + 1;
+ s->cols = xres;
+ DPRINTF("VGA_HTIM param, xres = %u!\n", s->cols);
+}
+
+static inline void ocfb_read_vtim(OCFBState *s, uint32_t val)
+{
+ /*uint32_t vsync_len = ((val >> 24) & 0xF) + 1;
+ uint32_t lower_margin = ((val >> 16) & 0xF) + 1;*/
+ uint32_t yres = (val & 0xFFFF) + 1;
+ s->rows = yres;
+ DPRINTF("VGA_VTIM param, yres = %u!\n", s->rows);
+}
+
+static void ocfb_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ OCFBState *s = (OCFBState *)opaque;
+
+ DPRINTF("write at 0x%08X 0x%08X\n",
+ (unsigned int)offset, (unsigned int)val);
+
+ switch (offset) {
+ case VGA_CTRL:
+ s->cr = val;
+
+ if ((s->cr & VGA_CTRL_CD) == VGA_CTRL_CD32) {
+ s->bpp = 32;
+ } else if ((s->cr & VGA_CTRL_CD) == VGA_CTRL_CD24) {
+ s->bpp = 32;
+ } else if ((s->cr & VGA_CTRL_CD) == VGA_CTRL_CD16) {
+ s->bpp = 16;
+ } else {
+ hw_error("Unsupported framebuffer color mode!\n");
+ }
+
+ ocfb_invalidate_display(s);
+ if (ocfb_enabled(s)) {
+ DPRINTF("Enable FB!\n");
+ ocfb_enable_console(s);
+ }
+
+ break;
+ case VGA_STAT:
+ DPRINTF("VGA_STAT param!\n");
+ break;
+ case VGA_HTIM:
+ ocfb_read_htim(s, val);
+ break;
+ case VGA_VTIM:
+ ocfb_read_vtim(s, val);
+ break;
+ case VGA_HVLEN:
+ DPRINTF("VGA_HVLEN param!\n");
+ break;
+ case VGA_VBARA:
+ DPRINTF("framebuffer@0x%08X!\n", (unsigned int)val);
+ s->fb = val;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset %x\n", __func__, (int)offset);
+ }
+}
+
+static const MemoryRegionOps ocfb_ops = {
+ .read = ocfb_read,
+ .write = ocfb_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static int vmstate_ocfb_post_load(void *opaque, int version_id)
+{
+ OCFBState *s = opaque;
+ /* Make sure we redraw, and at the right size */
+ ocfb_invalidate_display(s);
+ return 0;
+}
+
+static const GraphicHwOps ocfb_gfx_ops = {
+ .invalidate = ocfb_invalidate_display,
+ .gfx_update = ocfb_update_display,
+};
+
+static int ocfb_initfn(SysBusDevice *sbd)
+{
+ DeviceState *dev = DEVICE(sbd);
+ OCFBState *s = OCFB(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &ocfb_ops, s, "ocfb", 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+
+ s->con = graphic_console_init(dev, 0, &ocfb_gfx_ops, s);
+
+ return 0;
+}
+
+static void ocfb_init(Object *obj)
+{
+ OCFBState *s = OCFB(obj);
+
+ s->fb = 0;
+ s->cols = 0;
+ s->rows = 0;
+ s->bpp = 0;
+}
+
+static void ocfb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = ocfb_initfn;
+ set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
+ dc->vmsd = &vmstate_ocfb;
+}
+
+static const TypeInfo ocfb_info = {
+ .name = TYPE_OCFB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(OCFBState),
+ .instance_init = ocfb_init,
+ .class_init = ocfb_class_init,
+};
+
+static void ocfb_register_types(void)
+{
+ type_register_static(&ocfb_info);
+}
+
+type_init(ocfb_register_types)
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
index 80aa5ed..7752d22 100644
--- a/hw/openrisc/openrisc_asim.c
+++ b/hw/openrisc/openrisc_asim.c
@@ -44,13 +44,15 @@
enum {
OR_UART0,
OR_IDE,
- OR_OPENETH
+ OR_OPENETH,
+ OR_FRAMEBUFFER
};
static hwaddr mem_map[] = {
[OR_UART0] = 0x90000000,
[OR_IDE] = 0x9e000000,
[OR_OPENETH] = 0x92000000,
+ [OR_FRAMEBUFFER] = 0x91000000
};
@@ -183,6 +185,10 @@ static void openrisc_sim_init(MachineState *machine)
openrisc_sim_ide_init(get_system_memory(), mem_map[OR_IDE],
mem_map[OR_IDE] + 0x100, cpu->env.irq[15]);
+ /* OpenCores FrameBuffer device */
+ sysbus_create_simple("ocfb", mem_map[OR_FRAMEBUFFER], cpu->env.irq[8]);
+
+
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v3 2/4] hw/display: Add OpenCores FB device support
2014-10-05 11:05 ` [Qemu-devel] [PATCH v3 2/4] hw/display: Add OpenCores FB device support Valentin Manea
@ 2014-10-05 12:07 ` Jia Liu
0 siblings, 0 replies; 9+ messages in thread
From: Jia Liu @ 2014-10-05 12:07 UTC (permalink / raw)
To: Valentin Manea; +Cc: qemu-devel@nongnu.org, Stefan Hajnoczi
Hi Valentin,
On Sun, Oct 5, 2014 at 7:05 PM, Valentin Manea <valentin.manea@gmail.com> wrote:
> From edfd91e325a8c1806140c7468e187781d0b20ea9 Mon Sep 17 00:00:00 2001
> From: Valentin Manea <valentin.manea@gmail.com>
> Date: Sun, 21 Sep 2014 10:57:55 +0300
> Subject: [PATCH 2/4] target-openrisc: Add OpenCores FB device support
>
> Add support for the OpenCores Framebuffer device and enable it by
> default in the OpenRISC asim machine.
>
> The OpenCores display device is a simple open source framebuffer device
> created http://opencores.org/project,vgafb
>
> Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
> ---
> default-configs/or32-softmmu.mak | 2 +
> hw/display/Makefile.objs | 1 +
> hw/display/ocfb.c | 315 ++++++++++++++++++++++++++++++++++++++
> hw/display/ocfb.c.old | 321 +++++++++++++++++++++++++++++++++++++++
> hw/openrisc/openrisc_asim.c | 8 +-
> 5 files changed, 646 insertions(+), 1 deletion(-)
> create mode 100644 hw/display/ocfb.c
>
> diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
> index c3ff078..036f591 100644
> --- a/default-configs/or32-softmmu.mak
> +++ b/default-configs/or32-softmmu.mak
> @@ -5,3 +5,5 @@ CONFIG_OPENCORES_ETH=y
> CONFIG_IDE_CORE=y
> CONFIG_IDE_QDEV=y
> CONFIG_IDE_MMIO=y
> +CONFIG_FRAMEBUFFER=y
> +CONFIG_OPENCORESFB=y
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index 7ed76a9..4a755e6 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -33,3 +33,4 @@ obj-$(CONFIG_CG3) += cg3.o
> obj-$(CONFIG_VGA) += vga.o
>
> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
> +common-obj-$(CONFIG_OPENCORESFB) += ocfb.o
> diff --git a/hw/display/ocfb.c b/hw/display/ocfb.c
> new file mode 100644
> index 0000000..fb2b7df
> --- /dev/null
> +++ b/hw/display/ocfb.c
> @@ -0,0 +1,315 @@
> +/*
> + * OpenCores framebuffer device
> + *
> + * Copyright (c) 2014 Valentin Manea
> + * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
> + * Based on Arm PrimeCell PL110 Color LCD Controller by Paul Brook
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/sysbus.h"
> +#include "hw/display/framebuffer.h"
> +#include "ui/console.h"
> +
> +/* VGA defines */
> +#define VGA_CTRL 0x000
> +#define VGA_STAT 0x004
> +#define VGA_HTIM 0x008
> +#define VGA_VTIM 0x00c
> +#define VGA_HVLEN 0x010
> +#define VGA_VBARA 0x014
> +#define VGA_PALETTE 0x800
> +
> +#define VGA_CTRL_VEN 0x00000001 /* Video Enable */
> +#define VGA_CTRL_HIE 0x00000002 /* HSync Interrupt Enable */
> +#define VGA_CTRL_PC 0x00000800 /* 8-bit Pseudo Color Enable*/
> +#define VGA_CTRL_CD8 0x00000000 /* Color Depth 8 */
> +#define VGA_CTRL_CD16 0x00000200 /* Color Depth 16 */
> +#define VGA_CTRL_CD24 0x00000400 /* Color Depth 24 */
> +#define VGA_CTRL_CD32 0x00000600 /* Color Depth 32 */
> +#define VGA_CTRL_CD 0x00000E00 /* Color Depth Mask */
> +#define VGA_CTRL_VBL1 0x00000000 /* Burst Length 1 */
> +#define VGA_CTRL_VBL2 0x00000080 /* Burst Length 2 */
> +#define VGA_CTRL_VBL4 0x00000100 /* Burst Length 4 */
> +#define VGA_CTRL_VBL8 0x00000180 /* Burst Length 8 */
> +
> +#define PALETTE_SIZE 256
> +
> +#define TYPE_OCFB "ocfb"
> +#define OCFB(obj) OBJECT_CHECK(OCFBState, (obj), TYPE_OCFB)
> +
> +#ifdef DEBUG
> +#define DPRINTF(fmt, ...) \
> + do { printf("ocfb: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...)
> +#endif
> +
> +typedef struct OCFBState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + QemuConsole *con;
> + /* RAM fragment containing framebuffer */
> + MemoryRegionSection mem_section;
> + uint32_t cr;
> + hwaddr fb;
> + uint32_t fb_size;
> + uint32_t cols;
> + uint32_t rows;
> + uint32_t bpp;
> + uint32_t invalidate;
> + qemu_irq irq;
> +} OCFBState;
> +
> +static int vmstate_ocfb_post_load(void *opaque, int version_id);
> +
> +static const VMStateDescription vmstate_ocfb = {
> + .name = "ocfb",
> + .version_id = 2,
> + .minimum_version_id = 1,
> + .post_load = vmstate_ocfb_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(cr, OCFBState),
> + VMSTATE_UINT32(fb_size, OCFBState),
> + VMSTATE_UINT64(fb, OCFBState),
> + VMSTATE_UINT32(cols, OCFBState),
> + VMSTATE_UINT32(rows, OCFBState),
> + VMSTATE_UINT32(bpp, OCFBState),
> + VMSTATE_UINT32(invalidate, OCFBState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static int ocfb_enabled(OCFBState *s)
> +{
> + return s->cr & VGA_CTRL_VEN;
> +}
> +
> +static void ocfb_update_display(void *opaque)
> +{
> + OCFBState *s = (OCFBState *)opaque;
> +
> + if (!ocfb_enabled(s)) {
> + return;
> + }
> +
> + memory_region_sync_dirty_bitmap(s->mem_section.mr);
> +
> + int dirty = memory_region_get_dirty(s->mem_section.mr,
> + s->mem_section.offset_within_region, s->fb_size,
> + DIRTY_MEMORY_VGA);
> +
> + if (dirty || s->invalidate) {
> + dpy_gfx_update(s->con, 0, 0, s->cols, s->rows);
> + }
> + s->invalidate = 0;
> + memory_region_reset_dirty(s->mem_section.mr,
> + s->mem_section.offset_within_region, s->fb_size,
> + DIRTY_MEMORY_VGA);
> +}
> +
> +static void ocfb_invalidate_display(void *opaque)
> +{
> + OCFBState *s = (OCFBState *)opaque;
> + s->invalidate = 1;
> +}
> +
> +static void ocfb_ref_fb(OCFBState *s, hwaddr base, uint64_t src_len)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(s);
> +
> + memory_region_unref(s->mem_section.mr);
> + s->mem_section = memory_region_find(sysbus_address_space(sbd), base,
> + src_len);
> + assert(s->mem_section.mr);
> + assert(s->mem_section.offset_within_address_space == base);
> +
> + if (int128_get64(s->mem_section.size) != src_len ||
> + !memory_region_is_ram(s->mem_section.mr)) {
> + hw_error("Invalid framebuffer address!\n");
> + }
> +}
> +
> +static uint64_t ocfb_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + DPRINTF("read at 0x%08X\n", (unsigned int)offset);
> + return 0;
> +}
> +
> +
> +static void ocfb_enable_console(OCFBState *s)
> +{
> + DisplaySurface *surface;
> + if (!s->rows || !s->cols || !s->bpp) {
> + return;
> + }
> + if (!s->fb) {
> + return;
> + }
> + int stride = (s->cols * s->bpp) / 8;
> + s->fb_size = stride * s->rows;
> +
> + ocfb_ref_fb(s, s->fb, s->fb_size);
> +
> + pixman_format_code_t format = qemu_default_pixman_format(s->bpp, false);
> + /* console.c supported depth -> buffer can be used directly */
> + surface = qemu_create_displaysurface_guestmem(s->cols, s->rows, format,
> + 0, s->fb);
> + dpy_gfx_replace_surface(s->con, surface);
> +}
> +
> +static inline void ocfb_read_htim(OCFBState *s, uint32_t val)
> +{
> + /* uint32_t hsync_len = ((val >> 24) & 0xF) + 1;
> + uint32_t right_margin = ((val >> 16) & 0xF) + 1;*/
> + uint32_t xres = (val & 0xFFFF) + 1;
> + s->cols = xres;
> + DPRINTF("VGA_HTIM param, xres = %u!\n", s->cols);
> +}
> +
> +static inline void ocfb_read_vtim(OCFBState *s, uint32_t val)
> +{
> + /*uint32_t vsync_len = ((val >> 24) & 0xF) + 1;
> + uint32_t lower_margin = ((val >> 16) & 0xF) + 1;*/
> + uint32_t yres = (val & 0xFFFF) + 1;
> + s->rows = yres;
> + DPRINTF("VGA_VTIM param, yres = %u!\n", s->rows);
> +}
> +
> +static void ocfb_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + OCFBState *s = (OCFBState *)opaque;
> +
> + DPRINTF("write at 0x%08X 0x%08X\n",
> + (unsigned int)offset, (unsigned int)val);
> +
> + switch (offset) {
> + case VGA_CTRL:
> + s->cr = val;
> +
> + if ((s->cr & VGA_CTRL_CD) == VGA_CTRL_CD32) {
> + s->bpp = 32;
> + } else if ((s->cr & VGA_CTRL_CD) == VGA_CTRL_CD24) {
> + s->bpp = 32;
> + } else if ((s->cr & VGA_CTRL_CD) == VGA_CTRL_CD16) {
> + s->bpp = 16;
> + } else {
> + hw_error("Unsupported framebuffer color mode!\n");
> + }
> +
> + ocfb_invalidate_display(s);
> + if (ocfb_enabled(s)) {
> + DPRINTF("Enable FB!\n");
> + ocfb_enable_console(s);
> + }
> +
> + break;
> + case VGA_STAT:
> + DPRINTF("VGA_STAT param!\n");
> + break;
> + case VGA_HTIM:
> + ocfb_read_htim(s, val);
> + break;
> + case VGA_VTIM:
> + ocfb_read_vtim(s, val);
> + break;
> + case VGA_HVLEN:
> + DPRINTF("VGA_HVLEN param!\n");
> + break;
> + case VGA_VBARA:
> + DPRINTF("framebuffer@0x%08X!\n", (unsigned int)val);
> + s->fb = val;
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset %x\n", __func__, (int)offset);
> + }
> +}
> +
> +static const MemoryRegionOps ocfb_ops = {
> + .read = ocfb_read,
> + .write = ocfb_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static int vmstate_ocfb_post_load(void *opaque, int version_id)
> +{
> + OCFBState *s = opaque;
> + /* Make sure we redraw, and at the right size */
> + ocfb_invalidate_display(s);
> + return 0;
> +}
> +
> +static const GraphicHwOps ocfb_gfx_ops = {
> + .invalidate = ocfb_invalidate_display,
> + .gfx_update = ocfb_update_display,
> +};
> +
> +static int ocfb_initfn(SysBusDevice *sbd)
> +{
> + DeviceState *dev = DEVICE(sbd);
> + OCFBState *s = OCFB(dev);
> +
> + memory_region_init_io(&s->iomem, OBJECT(s), &ocfb_ops, s, "ocfb", 0x1000);
> + sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->irq);
> +
> + s->con = graphic_console_init(dev, 0, &ocfb_gfx_ops, s);
> +
> + return 0;
> +}
> +
> +static void ocfb_init(Object *obj)
> +{
> + OCFBState *s = OCFB(obj);
> +
> + s->fb = 0;
> + s->cols = 0;
> + s->rows = 0;
> + s->bpp = 0;
> +}
> +
> +static void ocfb_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> + k->init = ocfb_initfn;
> + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
> + dc->vmsd = &vmstate_ocfb;
> +}
> +
> +static const TypeInfo ocfb_info = {
> + .name = TYPE_OCFB,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(OCFBState),
> + .instance_init = ocfb_init,
> + .class_init = ocfb_class_init,
> +};
> +
> +static void ocfb_register_types(void)
> +{
> + type_register_static(&ocfb_info);
> +}
> +
> +type_init(ocfb_register_types)
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> index 80aa5ed..7752d22 100644
> --- a/hw/openrisc/openrisc_asim.c
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -44,13 +44,15 @@
> enum {
> OR_UART0,
> OR_IDE,
> - OR_OPENETH
> + OR_OPENETH,
> + OR_FRAMEBUFFER
> };
>
> static hwaddr mem_map[] = {
> [OR_UART0] = 0x90000000,
> [OR_IDE] = 0x9e000000,
> [OR_OPENETH] = 0x92000000,
> + [OR_FRAMEBUFFER] = 0x91000000
> };
>
>
> @@ -183,6 +185,10 @@ static void openrisc_sim_init(MachineState *machine)
> openrisc_sim_ide_init(get_system_memory(), mem_map[OR_IDE],
> mem_map[OR_IDE] + 0x100, cpu->env.irq[15]);
>
> + /* OpenCores FrameBuffer device */
> + sysbus_create_simple("ocfb", mem_map[OR_FRAMEBUFFER], cpu->env.irq[8]);
> +
> +
>
> cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> }
> --
> 1.9.1
>
>
Acked-by: Jia Liu <proljc@gmail.com>
Regards,
Jia
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 3/4] hw/input: Add OpenCores keyboard device support
2014-10-05 11:01 [Qemu-devel] [PATCH v3 0/4] target-openrisc: Machine improvements take three Valentin Manea
2014-10-05 11:03 ` [Qemu-devel] [PATCH v3 1/4] target-openrisc: New machine with IDE support Valentin Manea
2014-10-05 11:05 ` [Qemu-devel] [PATCH v3 2/4] hw/display: Add OpenCores FB device support Valentin Manea
@ 2014-10-05 11:06 ` Valentin Manea
2014-10-05 12:08 ` Jia Liu
2014-10-05 11:07 ` [Qemu-devel] [PATCH v3 4/4] hw/input: Add LPC32XX touchscreen device Valentin Manea
3 siblings, 1 reply; 9+ messages in thread
From: Valentin Manea @ 2014-10-05 11:06 UTC (permalink / raw)
To: qemu-devel@nongnu.org; +Cc: Jia Liu, Stefan Hajnoczi
Add support for the OpenCores keyboard device to the default OpenRisc
machine.
The OpenCores keyboard device is a simple open source keyboard device
created by the OpenCores project(http://opencores.org/). By default it
just forwards Linux like keycodes.
Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
---
default-configs/or32-softmmu.mak | 1 +
hw/input/Makefile.objs | 1 +
hw/input/ockbd.c | 165 +++++++++++++++++++++++++++++++++++++++
hw/openrisc/openrisc_asim.c | 9 ++-
4 files changed, 173 insertions(+), 3 deletions(-)
create mode 100644 hw/input/ockbd.c
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
index 036f591..9c8dad8 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -7,3 +7,4 @@ CONFIG_IDE_QDEV=y
CONFIG_IDE_MMIO=y
CONFIG_FRAMEBUFFER=y
CONFIG_OPENCORESFB=y
+CONFIG_OPENCORESKBD=y
diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
index e8c80b9..1179055 100644
--- a/hw/input/Makefile.objs
+++ b/hw/input/Makefile.objs
@@ -11,3 +11,4 @@ common-obj-$(CONFIG_VMMOUSE) += vmmouse.o
obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o
obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o
obj-$(CONFIG_TSC210X) += tsc210x.o
+obj-$(CONFIG_OPENCORESKBD) += ockbd.o
diff --git a/hw/input/ockbd.c b/hw/input/ockbd.c
new file mode 100644
index 0000000..64a6505
--- /dev/null
+++ b/hw/input/ockbd.c
@@ -0,0 +1,165 @@
+/*
+ * OpenCores Keyboard device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "ui/console.h"
+
+#define TYPE_OCKB "ockb"
+#define OCKB(obj) OBJECT_CHECK(OCKBState, (obj), TYPE_OCKB)
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) \
+ do { printf("ockb: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+typedef struct OCKBState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ qemu_irq irq;
+ uint8_t data[16];
+ uint32_t rptr, wptr, count;
+} OCKBState;
+
+
+static void ockb_keycode(void *opaque, int keycode)
+{
+ OCKBState *s = (OCKBState *) opaque;
+ /* The keycodes the driver expects are exactly the
+ same as we receive them */
+ if (s->count < sizeof(s->data)) {
+ s->data[s->wptr] = keycode;
+ if (++s->wptr == sizeof(s->data)) {
+ s->wptr = 0;
+ }
+ s->count++;
+ }
+ qemu_irq_raise(s->irq);
+}
+
+static uint64_t ockb_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ OCKBState *s = (OCKBState *) opaque;
+ int keycode;
+
+
+ if (offset >= 0x4) {
+ return 0;
+ }
+
+ DPRINTF("read offset %u\n", (uint32_t)offset);
+ if (s->count == 0) {
+ qemu_irq_lower(s->irq);
+ return 0;
+ }
+
+ keycode = s->data[s->rptr];
+ if (++s->rptr == sizeof(s->data)) {
+ s->rptr = 0;
+ }
+ s->count--;
+
+ return keycode;
+}
+
+static void ockb_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ /* Don't actually expect any write but don't fail */
+ DPRINTF("read offset %u\n", (uint32_t)offset);
+}
+
+static const MemoryRegionOps ockb_ops = {
+ .read = ockb_read,
+ .write = ockb_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int ockb_initfn(SysBusDevice *sbd)
+{
+ DeviceState *dev = DEVICE(sbd);
+ OCKBState *s = OCKB(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &ockb_ops, s, "ockb", 0x100);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+
+ qemu_add_kbd_event_handler(ockb_keycode, s);
+
+ return 0;
+}
+
+
+static const VMStateDescription vmstate_ockb_regs = {
+ .name = "ockb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8_ARRAY(data, OCKBState, 16),
+ VMSTATE_UINT32(rptr, OCKBState),
+ VMSTATE_UINT32(wptr, OCKBState),
+ VMSTATE_UINT32(count, OCKBState),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static void ockb_init(Object *obj)
+{
+ OCKBState *s = OCKB(obj);
+
+ memset(s->data, 0, sizeof(s->data));
+ s->rptr = 0;
+ s->wptr = 0;
+ s->count = 0;
+}
+
+static void ockb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = ockb_initfn;
+ dc->desc = "OpenCores Keyboard controller";
+ dc->vmsd = &vmstate_ockb_regs;
+}
+
+static const TypeInfo ockb_info = {
+ .name = TYPE_OCKB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(OCKBState),
+ .instance_init = ockb_init,
+ .class_init = ockb_class_init,
+};
+
+static void ockb_register_types(void)
+{
+ type_register_static(&ockb_info);
+}
+
+type_init(ockb_register_types)
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
index 7752d22..05b59e8 100644
--- a/hw/openrisc/openrisc_asim.c
+++ b/hw/openrisc/openrisc_asim.c
@@ -45,14 +45,16 @@ enum {
OR_UART0,
OR_IDE,
OR_OPENETH,
- OR_FRAMEBUFFER
+ OR_FRAMEBUFFER,
+ OR_KEYBOARD,
};
static hwaddr mem_map[] = {
[OR_UART0] = 0x90000000,
[OR_IDE] = 0x9e000000,
[OR_OPENETH] = 0x92000000,
- [OR_FRAMEBUFFER] = 0x91000000
+ [OR_FRAMEBUFFER] = 0x91000000,
+ [OR_KEYBOARD] = 0x94000000,
};
@@ -188,7 +190,8 @@ static void openrisc_sim_init(MachineState *machine)
/* OpenCores FrameBuffer device */
sysbus_create_simple("ocfb", mem_map[OR_FRAMEBUFFER], cpu->env.irq[8]);
-
+ /* OpenCores keyboard */
+ sysbus_create_simple("ockb", mem_map[OR_KEYBOARD], cpu->env.irq[5]);
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v3 3/4] hw/input: Add OpenCores keyboard device support
2014-10-05 11:06 ` [Qemu-devel] [PATCH v3 3/4] hw/input: Add OpenCores keyboard " Valentin Manea
@ 2014-10-05 12:08 ` Jia Liu
0 siblings, 0 replies; 9+ messages in thread
From: Jia Liu @ 2014-10-05 12:08 UTC (permalink / raw)
To: Valentin Manea; +Cc: qemu-devel@nongnu.org, Stefan Hajnoczi
Hi Valentin,
On Sun, Oct 5, 2014 at 7:06 PM, Valentin Manea <valentin.manea@gmail.com> wrote:
> Add support for the OpenCores keyboard device to the default OpenRisc
> machine.
>
> The OpenCores keyboard device is a simple open source keyboard device
> created by the OpenCores project(http://opencores.org/). By default it
> just forwards Linux like keycodes.
>
> Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
> ---
> default-configs/or32-softmmu.mak | 1 +
> hw/input/Makefile.objs | 1 +
> hw/input/ockbd.c | 165 +++++++++++++++++++++++++++++++++++++++
> hw/openrisc/openrisc_asim.c | 9 ++-
> 4 files changed, 173 insertions(+), 3 deletions(-)
> create mode 100644 hw/input/ockbd.c
>
> diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
> index 036f591..9c8dad8 100644
> --- a/default-configs/or32-softmmu.mak
> +++ b/default-configs/or32-softmmu.mak
> @@ -7,3 +7,4 @@ CONFIG_IDE_QDEV=y
> CONFIG_IDE_MMIO=y
> CONFIG_FRAMEBUFFER=y
> CONFIG_OPENCORESFB=y
> +CONFIG_OPENCORESKBD=y
> diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
> index e8c80b9..1179055 100644
> --- a/hw/input/Makefile.objs
> +++ b/hw/input/Makefile.objs
> @@ -11,3 +11,4 @@ common-obj-$(CONFIG_VMMOUSE) += vmmouse.o
> obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o
> obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o
> obj-$(CONFIG_TSC210X) += tsc210x.o
> +obj-$(CONFIG_OPENCORESKBD) += ockbd.o
> diff --git a/hw/input/ockbd.c b/hw/input/ockbd.c
> new file mode 100644
> index 0000000..64a6505
> --- /dev/null
> +++ b/hw/input/ockbd.c
> @@ -0,0 +1,165 @@
> +/*
> + * OpenCores Keyboard device
> + *
> + * Copyright (c) 2014 Valentin Manea
> + * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "ui/console.h"
> +
> +#define TYPE_OCKB "ockb"
> +#define OCKB(obj) OBJECT_CHECK(OCKBState, (obj), TYPE_OCKB)
> +
> +#ifdef DEBUG
> +#define DPRINTF(fmt, ...) \
> + do { printf("ockb: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...)
> +#endif
> +
> +typedef struct OCKBState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + qemu_irq irq;
> + uint8_t data[16];
> + uint32_t rptr, wptr, count;
> +} OCKBState;
> +
> +
> +static void ockb_keycode(void *opaque, int keycode)
> +{
> + OCKBState *s = (OCKBState *) opaque;
> + /* The keycodes the driver expects are exactly the
> + same as we receive them */
> + if (s->count < sizeof(s->data)) {
> + s->data[s->wptr] = keycode;
> + if (++s->wptr == sizeof(s->data)) {
> + s->wptr = 0;
> + }
> + s->count++;
> + }
> + qemu_irq_raise(s->irq);
> +}
> +
> +static uint64_t ockb_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + OCKBState *s = (OCKBState *) opaque;
> + int keycode;
> +
> +
> + if (offset >= 0x4) {
> + return 0;
> + }
> +
> + DPRINTF("read offset %u\n", (uint32_t)offset);
> + if (s->count == 0) {
> + qemu_irq_lower(s->irq);
> + return 0;
> + }
> +
> + keycode = s->data[s->rptr];
> + if (++s->rptr == sizeof(s->data)) {
> + s->rptr = 0;
> + }
> + s->count--;
> +
> + return keycode;
> +}
> +
> +static void ockb_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + /* Don't actually expect any write but don't fail */
> + DPRINTF("read offset %u\n", (uint32_t)offset);
> +}
> +
> +static const MemoryRegionOps ockb_ops = {
> + .read = ockb_read,
> + .write = ockb_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static int ockb_initfn(SysBusDevice *sbd)
> +{
> + DeviceState *dev = DEVICE(sbd);
> + OCKBState *s = OCKB(dev);
> +
> + memory_region_init_io(&s->iomem, OBJECT(s), &ockb_ops, s, "ockb", 0x100);
> + sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->irq);
> +
> + qemu_add_kbd_event_handler(ockb_keycode, s);
> +
> + return 0;
> +}
> +
> +
> +static const VMStateDescription vmstate_ockb_regs = {
> + .name = "ockb",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT8_ARRAY(data, OCKBState, 16),
> + VMSTATE_UINT32(rptr, OCKBState),
> + VMSTATE_UINT32(wptr, OCKBState),
> + VMSTATE_UINT32(count, OCKBState),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> +static void ockb_init(Object *obj)
> +{
> + OCKBState *s = OCKB(obj);
> +
> + memset(s->data, 0, sizeof(s->data));
> + s->rptr = 0;
> + s->wptr = 0;
> + s->count = 0;
> +}
> +
> +static void ockb_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> + k->init = ockb_initfn;
> + dc->desc = "OpenCores Keyboard controller";
> + dc->vmsd = &vmstate_ockb_regs;
> +}
> +
> +static const TypeInfo ockb_info = {
> + .name = TYPE_OCKB,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(OCKBState),
> + .instance_init = ockb_init,
> + .class_init = ockb_class_init,
> +};
> +
> +static void ockb_register_types(void)
> +{
> + type_register_static(&ockb_info);
> +}
> +
> +type_init(ockb_register_types)
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> index 7752d22..05b59e8 100644
> --- a/hw/openrisc/openrisc_asim.c
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -45,14 +45,16 @@ enum {
> OR_UART0,
> OR_IDE,
> OR_OPENETH,
> - OR_FRAMEBUFFER
> + OR_FRAMEBUFFER,
> + OR_KEYBOARD,
> };
>
> static hwaddr mem_map[] = {
> [OR_UART0] = 0x90000000,
> [OR_IDE] = 0x9e000000,
> [OR_OPENETH] = 0x92000000,
> - [OR_FRAMEBUFFER] = 0x91000000
> + [OR_FRAMEBUFFER] = 0x91000000,
> + [OR_KEYBOARD] = 0x94000000,
> };
>
>
> @@ -188,7 +190,8 @@ static void openrisc_sim_init(MachineState *machine)
> /* OpenCores FrameBuffer device */
> sysbus_create_simple("ocfb", mem_map[OR_FRAMEBUFFER], cpu->env.irq[8]);
>
> -
> + /* OpenCores keyboard */
> + sysbus_create_simple("ockb", mem_map[OR_KEYBOARD], cpu->env.irq[5]);
>
> cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> }
> --
> 1.9.1
>
>
Acked-by: Jia Liu <proljc@gmail.com>
Regards,
Jia
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 4/4] hw/input: Add LPC32XX touchscreen device
2014-10-05 11:01 [Qemu-devel] [PATCH v3 0/4] target-openrisc: Machine improvements take three Valentin Manea
` (2 preceding siblings ...)
2014-10-05 11:06 ` [Qemu-devel] [PATCH v3 3/4] hw/input: Add OpenCores keyboard " Valentin Manea
@ 2014-10-05 11:07 ` Valentin Manea
2014-10-05 12:08 ` Jia Liu
3 siblings, 1 reply; 9+ messages in thread
From: Valentin Manea @ 2014-10-05 11:07 UTC (permalink / raw)
To: qemu-devel@nongnu.org; +Cc: Jia Liu, Stefan Hajnoczi
The LPC32XX is a simple MMIO touch screen device with a Linux device
driver. The device is suitable for small machines which require mouse
input but have no suitable bus(SPI, I2C).
Add the LPC32XX device to the default OpenRisc machine.
Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
---
default-configs/or32-softmmu.mak | 1 +
hw/input/Makefile.objs | 1 +
hw/input/lpc32xx.c | 273 +++++++++++++++++++++++++++++++++++++++
hw/openrisc/openrisc_asim.c | 5 +
4 files changed, 280 insertions(+)
create mode 100644 hw/input/lpc32xx.c
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
index 9c8dad8..e4d63a0 100644
--- a/default-configs/or32-softmmu.mak
+++ b/default-configs/or32-softmmu.mak
@@ -8,3 +8,4 @@ CONFIG_IDE_MMIO=y
CONFIG_FRAMEBUFFER=y
CONFIG_OPENCORESFB=y
CONFIG_OPENCORESKBD=y
+CONFIG_LPC32XX=y
diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
index 1179055..4e732b5 100644
--- a/hw/input/Makefile.objs
+++ b/hw/input/Makefile.objs
@@ -12,3 +12,4 @@ obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o
obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o
obj-$(CONFIG_TSC210X) += tsc210x.o
obj-$(CONFIG_OPENCORESKBD) += ockbd.o
+obj-$(CONFIG_LPC32XX) += lpc32xx.o
diff --git a/hw/input/lpc32xx.c b/hw/input/lpc32xx.c
new file mode 100644
index 0000000..e51e189
--- /dev/null
+++ b/hw/input/lpc32xx.c
@@ -0,0 +1,273 @@
+/*
+ * OpenCores framebuffer device
+ *
+ * Copyright (c) 2014 Valentin Manea
+ * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "ui/console.h"
+#include "ui/input.h"
+#include "qemu/timer.h"
+
+/*
+ * Touchscreen controller register offsets
+ */
+#define LPC32XX_TSC_STAT 0x00
+#define LPC32XX_TSC_SEL 0x04
+#define LPC32XX_TSC_CON 0x08
+#define LPC32XX_TSC_FIFO 0x0C
+#define LPC32XX_TSC_DTR 0x10
+#define LPC32XX_TSC_RTR 0x14
+#define LPC32XX_TSC_UTR 0x18
+#define LPC32XX_TSC_TTR 0x1C
+#define LPC32XX_TSC_DXP 0x20
+#define LPC32XX_TSC_MIN_X 0x24
+#define LPC32XX_TSC_MAX_X 0x28
+#define LPC32XX_TSC_MIN_Y 0x2C
+#define LPC32XX_TSC_MAX_Y 0x30
+#define LPC32XX_TSC_AUX_UTR 0x34
+#define LPC32XX_TSC_AUX_MIN 0x38
+#define LPC32XX_TSC_AUX_MAX 0x3C
+
+#define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
+#define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
+#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
+
+#define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
+#define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
+
+#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
+
+#define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
+#define LPC32XX_TSC_FIFO_X_VAL(x) (((LPC32XX_TSC_ADCDAT_VALUE_MASK - x) & \
+ LPC32XX_TSC_ADCDAT_VALUE_MASK) << 16)
+#define LPC32XX_TSC_FIFO_Y_VAL(y) ((LPC32XX_TSC_ADCDAT_VALUE_MASK - y) & \
+ LPC32XX_TSC_ADCDAT_VALUE_MASK)
+
+
+#define LPC32XX_TSC_MIN_XY_VAL 0x0
+#define LPC32XX_TSC_MAX_XY_VAL 0x3FF
+
+
+#define TYPE_LPC32XX "lpc32xx"
+#define LPC32XX(obj) OBJECT_CHECK(LPC32XXState, (obj), TYPE_LPC32XX)
+
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) \
+ do { printf("lpc32xx: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+
+typedef struct LPC32XXState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ qemu_irq irq;
+ uint32_t control;
+ uint32_t status;
+ bool pressed;
+ uint32_t move_count;
+ uint32_t fifo;
+ int32_t fifo_size;
+} LPC32XXState;
+
+static const VMStateDescription vmstate_lpc32xx = {
+ .name = "lpc32xx",
+ .version_id = 2,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(control, LPC32XXState),
+ VMSTATE_UINT32(status, LPC32XXState),
+ VMSTATE_UINT32(move_count, LPC32XXState),
+ VMSTATE_UINT32(fifo, LPC32XXState),
+ VMSTATE_INT32(fifo_size, LPC32XXState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+
+static int lpc32xx_enabled(LPC32XXState *s)
+{
+ return s->control & LPC32XX_TSC_ADCCON_AUTO_EN;
+}
+
+static uint64_t lpc32xx_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ LPC32XXState *s = (LPC32XXState *)opaque;
+ DPRINTF("read at 0x%08X\n", (unsigned int)offset);
+ switch (offset) {
+ case LPC32XX_TSC_CON:
+ return s->control;
+ case LPC32XX_TSC_STAT:
+ qemu_irq_lower(s->irq);
+ return s->status;
+ case LPC32XX_TSC_FIFO:
+ if (s->fifo_size <= 0) {
+ s->status |= LPC32XX_TSC_STAT_FIFO_EMPTY;
+ } else {
+ s->fifo_size--;
+ }
+ return s->fifo;
+ }
+ return 0;
+}
+
+static void lpc32xx_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ LPC32XXState *s = (LPC32XXState *)opaque;
+
+ DPRINTF("write at 0x%08X 0x%08X\n", (uint32_t)offset, (uint32_t)val);
+ switch (offset) {
+ case LPC32XX_TSC_CON:
+ s->control = val;
+ break;
+ break;
+ case LPC32XX_TSC_SEL:
+ case LPC32XX_TSC_MIN_X:
+ case LPC32XX_TSC_MAX_X:
+ case LPC32XX_TSC_MIN_Y:
+ case LPC32XX_TSC_MAX_Y:
+ case LPC32XX_TSC_AUX_UTR:
+ case LPC32XX_TSC_AUX_MIN:
+ case LPC32XX_TSC_AUX_MAX:
+ case LPC32XX_TSC_RTR:
+ case LPC32XX_TSC_DTR:
+ case LPC32XX_TSC_TTR:
+ case LPC32XX_TSC_DXP:
+ case LPC32XX_TSC_UTR:
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "lpc32xx: Bad offset %x\n", (int)offset);
+ }
+}
+
+static void lpc32xx_touchscreen_event(void *opaque,
+ int x, int y, int z, int buttons_state)
+{
+ LPC32XXState *s = (LPC32XXState *)opaque;
+ /* Current driver has LPC32XX_TSC_MAX_XY_VAL hardcoded */
+ x = qemu_input_scale_axis(x, INPUT_EVENT_ABS_SIZE, LPC32XX_TSC_MAX_XY_VAL);
+ y = qemu_input_scale_axis(y, INPUT_EVENT_ABS_SIZE, LPC32XX_TSC_MAX_XY_VAL);
+
+ DPRINTF("event %d %d %d\n", x, y, buttons_state);
+ if (!lpc32xx_enabled(s)) {
+ return;
+ }
+
+ if (!buttons_state) {
+ /* Finger up */
+ if (s->pressed) {
+ s->status &= ~LPC32XX_TSC_STAT_FIFO_EMPTY;
+ /* just a button up event */
+ s->fifo_size = 0;
+ s->fifo = LPC32XX_TSC_FIFO_TS_P_LEVEL;
+ s->pressed = false;
+ qemu_irq_raise(s->irq);
+ return;
+ }
+ /* Just mouse move */
+ else {
+ return;
+ }
+ }
+
+ /* Move */
+ if (buttons_state && s->pressed) {
+ s->move_count++;
+ /* handle mouse move only every fourth time */
+ if (s->move_count & 3) {
+ return;
+ }
+ }
+
+ s->status &= ~LPC32XX_TSC_STAT_FIFO_EMPTY;
+ s->fifo_size = 4;
+ s->fifo = LPC32XX_TSC_FIFO_X_VAL(x);
+ s->fifo |= LPC32XX_TSC_FIFO_Y_VAL(y);
+ s->pressed = true;
+ qemu_irq_raise(s->irq);
+}
+
+static const MemoryRegionOps lpc32xx_ops = {
+ .read = lpc32xx_read,
+ .write = lpc32xx_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int lpc32xx_initfn(SysBusDevice *sbd)
+{
+ DeviceState *dev = DEVICE(sbd);
+ LPC32XXState *s = LPC32XX(dev);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &lpc32xx_ops,
+ s, "lpc32xx", 0x100);
+ sysbus_init_mmio(sbd, &s->iomem);
+
+ sysbus_init_irq(sbd, &s->irq);
+ qemu_add_mouse_event_handler(lpc32xx_touchscreen_event, s, 1,
+ "QEMU LPC32XX-driven Touchscreen");
+
+ return 0;
+}
+
+static void lpc32xx_init(Object *obj)
+{
+ LPC32XXState *s = LPC32XX(obj);
+ s->control = 0x0;
+ s->status = LPC32XX_TSC_STAT_FIFO_EMPTY;
+ s->pressed = false;
+ s->move_count = 0;
+ s->fifo = 0;
+ s->fifo_size = 0;
+}
+
+static void lpc32xx_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = lpc32xx_initfn;
+ dc->vmsd = &vmstate_lpc32xx;
+}
+
+static const TypeInfo lpc32xx_info = {
+ .name = TYPE_LPC32XX,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(LPC32XXState),
+ .instance_init = lpc32xx_init,
+ .class_init = lpc32xx_class_init,
+};
+
+static void lpc32xx_register_types(void)
+{
+ type_register_static(&lpc32xx_info);
+}
+
+type_init(lpc32xx_register_types)
diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
index 05b59e8..2199a63 100644
--- a/hw/openrisc/openrisc_asim.c
+++ b/hw/openrisc/openrisc_asim.c
@@ -47,6 +47,7 @@ enum {
OR_OPENETH,
OR_FRAMEBUFFER,
OR_KEYBOARD,
+ OR_TOUCHSCREEN,
};
static hwaddr mem_map[] = {
@@ -55,6 +56,7 @@ static hwaddr mem_map[] = {
[OR_OPENETH] = 0x92000000,
[OR_FRAMEBUFFER] = 0x91000000,
[OR_KEYBOARD] = 0x94000000,
+ [OR_TOUCHSCREEN] = 0x93000000,
};
@@ -193,6 +195,9 @@ static void openrisc_sim_init(MachineState *machine)
/* OpenCores keyboard */
sysbus_create_simple("ockb", mem_map[OR_KEYBOARD], cpu->env.irq[5]);
+ /* LPC32XX Touch Screen */
+ sysbus_create_simple("lpc32xx", mem_map[OR_TOUCHSCREEN], cpu->env.irq[9]);
+
cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [Qemu-devel] [PATCH v3 4/4] hw/input: Add LPC32XX touchscreen device
2014-10-05 11:07 ` [Qemu-devel] [PATCH v3 4/4] hw/input: Add LPC32XX touchscreen device Valentin Manea
@ 2014-10-05 12:08 ` Jia Liu
0 siblings, 0 replies; 9+ messages in thread
From: Jia Liu @ 2014-10-05 12:08 UTC (permalink / raw)
To: Valentin Manea; +Cc: qemu-devel@nongnu.org, Stefan Hajnoczi
Hi Valentin,
On Sun, Oct 5, 2014 at 7:07 PM, Valentin Manea <valentin.manea@gmail.com> wrote:
> The LPC32XX is a simple MMIO touch screen device with a Linux device
> driver. The device is suitable for small machines which require mouse
> input but have no suitable bus(SPI, I2C).
>
> Add the LPC32XX device to the default OpenRisc machine.
>
> Signed-off-by: Valentin Manea <valentin.manea@gmail.com>
> ---
> default-configs/or32-softmmu.mak | 1 +
> hw/input/Makefile.objs | 1 +
> hw/input/lpc32xx.c | 273 +++++++++++++++++++++++++++++++++++++++
> hw/openrisc/openrisc_asim.c | 5 +
> 4 files changed, 280 insertions(+)
> create mode 100644 hw/input/lpc32xx.c
>
> diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
> index 9c8dad8..e4d63a0 100644
> --- a/default-configs/or32-softmmu.mak
> +++ b/default-configs/or32-softmmu.mak
> @@ -8,3 +8,4 @@ CONFIG_IDE_MMIO=y
> CONFIG_FRAMEBUFFER=y
> CONFIG_OPENCORESFB=y
> CONFIG_OPENCORESKBD=y
> +CONFIG_LPC32XX=y
> diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
> index 1179055..4e732b5 100644
> --- a/hw/input/Makefile.objs
> +++ b/hw/input/Makefile.objs
> @@ -12,3 +12,4 @@ obj-$(CONFIG_MILKYMIST) += milkymist-softusb.o
> obj-$(CONFIG_PXA2XX) += pxa2xx_keypad.o
> obj-$(CONFIG_TSC210X) += tsc210x.o
> obj-$(CONFIG_OPENCORESKBD) += ockbd.o
> +obj-$(CONFIG_LPC32XX) += lpc32xx.o
> diff --git a/hw/input/lpc32xx.c b/hw/input/lpc32xx.c
> new file mode 100644
> index 0000000..e51e189
> --- /dev/null
> +++ b/hw/input/lpc32xx.c
> @@ -0,0 +1,273 @@
> +/*
> + * OpenCores framebuffer device
> + *
> + * Copyright (c) 2014 Valentin Manea
> + * Based on work by Sebastian Macke for jor1k http://s-macke.github.io/jor1k/
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/devices.h"
> +#include "ui/console.h"
> +#include "ui/input.h"
> +#include "qemu/timer.h"
> +
> +/*
> + * Touchscreen controller register offsets
> + */
> +#define LPC32XX_TSC_STAT 0x00
> +#define LPC32XX_TSC_SEL 0x04
> +#define LPC32XX_TSC_CON 0x08
> +#define LPC32XX_TSC_FIFO 0x0C
> +#define LPC32XX_TSC_DTR 0x10
> +#define LPC32XX_TSC_RTR 0x14
> +#define LPC32XX_TSC_UTR 0x18
> +#define LPC32XX_TSC_TTR 0x1C
> +#define LPC32XX_TSC_DXP 0x20
> +#define LPC32XX_TSC_MIN_X 0x24
> +#define LPC32XX_TSC_MAX_X 0x28
> +#define LPC32XX_TSC_MIN_Y 0x2C
> +#define LPC32XX_TSC_MAX_Y 0x30
> +#define LPC32XX_TSC_AUX_UTR 0x34
> +#define LPC32XX_TSC_AUX_MIN 0x38
> +#define LPC32XX_TSC_AUX_MAX 0x3C
> +
> +#define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
> +#define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
> +#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
> +
> +#define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
> +#define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
> +
> +#define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
> +
> +#define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
> +#define LPC32XX_TSC_FIFO_X_VAL(x) (((LPC32XX_TSC_ADCDAT_VALUE_MASK - x) & \
> + LPC32XX_TSC_ADCDAT_VALUE_MASK) << 16)
> +#define LPC32XX_TSC_FIFO_Y_VAL(y) ((LPC32XX_TSC_ADCDAT_VALUE_MASK - y) & \
> + LPC32XX_TSC_ADCDAT_VALUE_MASK)
> +
> +
> +#define LPC32XX_TSC_MIN_XY_VAL 0x0
> +#define LPC32XX_TSC_MAX_XY_VAL 0x3FF
> +
> +
> +#define TYPE_LPC32XX "lpc32xx"
> +#define LPC32XX(obj) OBJECT_CHECK(LPC32XXState, (obj), TYPE_LPC32XX)
> +
> +
> +#ifdef DEBUG
> +#define DPRINTF(fmt, ...) \
> + do { printf("lpc32xx: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...)
> +#endif
> +
> +
> +typedef struct LPC32XXState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + qemu_irq irq;
> + uint32_t control;
> + uint32_t status;
> + bool pressed;
> + uint32_t move_count;
> + uint32_t fifo;
> + int32_t fifo_size;
> +} LPC32XXState;
> +
> +static const VMStateDescription vmstate_lpc32xx = {
> + .name = "lpc32xx",
> + .version_id = 2,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(control, LPC32XXState),
> + VMSTATE_UINT32(status, LPC32XXState),
> + VMSTATE_UINT32(move_count, LPC32XXState),
> + VMSTATE_UINT32(fifo, LPC32XXState),
> + VMSTATE_INT32(fifo_size, LPC32XXState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +
> +static int lpc32xx_enabled(LPC32XXState *s)
> +{
> + return s->control & LPC32XX_TSC_ADCCON_AUTO_EN;
> +}
> +
> +static uint64_t lpc32xx_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + LPC32XXState *s = (LPC32XXState *)opaque;
> + DPRINTF("read at 0x%08X\n", (unsigned int)offset);
> + switch (offset) {
> + case LPC32XX_TSC_CON:
> + return s->control;
> + case LPC32XX_TSC_STAT:
> + qemu_irq_lower(s->irq);
> + return s->status;
> + case LPC32XX_TSC_FIFO:
> + if (s->fifo_size <= 0) {
> + s->status |= LPC32XX_TSC_STAT_FIFO_EMPTY;
> + } else {
> + s->fifo_size--;
> + }
> + return s->fifo;
> + }
> + return 0;
> +}
> +
> +static void lpc32xx_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + LPC32XXState *s = (LPC32XXState *)opaque;
> +
> + DPRINTF("write at 0x%08X 0x%08X\n", (uint32_t)offset, (uint32_t)val);
> + switch (offset) {
> + case LPC32XX_TSC_CON:
> + s->control = val;
> + break;
> + break;
> + case LPC32XX_TSC_SEL:
> + case LPC32XX_TSC_MIN_X:
> + case LPC32XX_TSC_MAX_X:
> + case LPC32XX_TSC_MIN_Y:
> + case LPC32XX_TSC_MAX_Y:
> + case LPC32XX_TSC_AUX_UTR:
> + case LPC32XX_TSC_AUX_MIN:
> + case LPC32XX_TSC_AUX_MAX:
> + case LPC32XX_TSC_RTR:
> + case LPC32XX_TSC_DTR:
> + case LPC32XX_TSC_TTR:
> + case LPC32XX_TSC_DXP:
> + case LPC32XX_TSC_UTR:
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "lpc32xx: Bad offset %x\n", (int)offset);
> + }
> +}
> +
> +static void lpc32xx_touchscreen_event(void *opaque,
> + int x, int y, int z, int buttons_state)
> +{
> + LPC32XXState *s = (LPC32XXState *)opaque;
> + /* Current driver has LPC32XX_TSC_MAX_XY_VAL hardcoded */
> + x = qemu_input_scale_axis(x, INPUT_EVENT_ABS_SIZE, LPC32XX_TSC_MAX_XY_VAL);
> + y = qemu_input_scale_axis(y, INPUT_EVENT_ABS_SIZE, LPC32XX_TSC_MAX_XY_VAL);
> +
> + DPRINTF("event %d %d %d\n", x, y, buttons_state);
> + if (!lpc32xx_enabled(s)) {
> + return;
> + }
> +
> + if (!buttons_state) {
> + /* Finger up */
> + if (s->pressed) {
> + s->status &= ~LPC32XX_TSC_STAT_FIFO_EMPTY;
> + /* just a button up event */
> + s->fifo_size = 0;
> + s->fifo = LPC32XX_TSC_FIFO_TS_P_LEVEL;
> + s->pressed = false;
> + qemu_irq_raise(s->irq);
> + return;
> + }
> + /* Just mouse move */
> + else {
> + return;
> + }
> + }
> +
> + /* Move */
> + if (buttons_state && s->pressed) {
> + s->move_count++;
> + /* handle mouse move only every fourth time */
> + if (s->move_count & 3) {
> + return;
> + }
> + }
> +
> + s->status &= ~LPC32XX_TSC_STAT_FIFO_EMPTY;
> + s->fifo_size = 4;
> + s->fifo = LPC32XX_TSC_FIFO_X_VAL(x);
> + s->fifo |= LPC32XX_TSC_FIFO_Y_VAL(y);
> + s->pressed = true;
> + qemu_irq_raise(s->irq);
> +}
> +
> +static const MemoryRegionOps lpc32xx_ops = {
> + .read = lpc32xx_read,
> + .write = lpc32xx_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static int lpc32xx_initfn(SysBusDevice *sbd)
> +{
> + DeviceState *dev = DEVICE(sbd);
> + LPC32XXState *s = LPC32XX(dev);
> +
> + memory_region_init_io(&s->iomem, OBJECT(s), &lpc32xx_ops,
> + s, "lpc32xx", 0x100);
> + sysbus_init_mmio(sbd, &s->iomem);
> +
> + sysbus_init_irq(sbd, &s->irq);
> + qemu_add_mouse_event_handler(lpc32xx_touchscreen_event, s, 1,
> + "QEMU LPC32XX-driven Touchscreen");
> +
> + return 0;
> +}
> +
> +static void lpc32xx_init(Object *obj)
> +{
> + LPC32XXState *s = LPC32XX(obj);
> + s->control = 0x0;
> + s->status = LPC32XX_TSC_STAT_FIFO_EMPTY;
> + s->pressed = false;
> + s->move_count = 0;
> + s->fifo = 0;
> + s->fifo_size = 0;
> +}
> +
> +static void lpc32xx_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> + k->init = lpc32xx_initfn;
> + dc->vmsd = &vmstate_lpc32xx;
> +}
> +
> +static const TypeInfo lpc32xx_info = {
> + .name = TYPE_LPC32XX,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(LPC32XXState),
> + .instance_init = lpc32xx_init,
> + .class_init = lpc32xx_class_init,
> +};
> +
> +static void lpc32xx_register_types(void)
> +{
> + type_register_static(&lpc32xx_info);
> +}
> +
> +type_init(lpc32xx_register_types)
> diff --git a/hw/openrisc/openrisc_asim.c b/hw/openrisc/openrisc_asim.c
> index 05b59e8..2199a63 100644
> --- a/hw/openrisc/openrisc_asim.c
> +++ b/hw/openrisc/openrisc_asim.c
> @@ -47,6 +47,7 @@ enum {
> OR_OPENETH,
> OR_FRAMEBUFFER,
> OR_KEYBOARD,
> + OR_TOUCHSCREEN,
> };
>
> static hwaddr mem_map[] = {
> @@ -55,6 +56,7 @@ static hwaddr mem_map[] = {
> [OR_OPENETH] = 0x92000000,
> [OR_FRAMEBUFFER] = 0x91000000,
> [OR_KEYBOARD] = 0x94000000,
> + [OR_TOUCHSCREEN] = 0x93000000,
> };
>
>
> @@ -193,6 +195,9 @@ static void openrisc_sim_init(MachineState *machine)
> /* OpenCores keyboard */
> sysbus_create_simple("ockb", mem_map[OR_KEYBOARD], cpu->env.irq[5]);
>
> + /* LPC32XX Touch Screen */
> + sysbus_create_simple("lpc32xx", mem_map[OR_TOUCHSCREEN], cpu->env.irq[9]);
> +
> cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu);
> }
>
> --
> 1.9.1
>
>
Acked-by: Jia Liu <proljc@gmail.com>
Regards,
Jia
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