From: Alexander Graf <agraf@suse.de>
To: Aravinda Prasad <aravinda@linux.vnet.ibm.com>
Cc: benh@au1.ibm.com, aik@au1.ibm.com, qemu-devel@nongnu.org,
qemu-ppc@nongnu.org, paulus@samba.org
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 4/5] target-ppc: Handle ibm, nmi-register RTAS call
Date: Mon, 06 Oct 2014 11:40:30 +0200 [thread overview]
Message-ID: <5432638E.2000803@suse.de> (raw)
In-Reply-To: <54323782.8060804@linux.vnet.ibm.com>
On 06.10.14 08:32, Aravinda Prasad wrote:
>
>
> On Monday 08 September 2014 02:17 AM, Alexander Graf wrote:
>>
>>
>> On 25.08.14 15:45, Aravinda Prasad wrote:
>>> This patch adds FWNMI support in qemu for powerKVM
>>> guests by handling the ibm,nmi-register rtas call.
>>> Whenever OS issues ibm,nmi-register RTAS call, the
>>> machine check notification address is saved and the
>>> machine check interrupt vector 0x200 is patched to
>>> issue a private hcall.
>>>
>>> Signed-off-by: Aravinda Prasad <aravinda@linux.vnet.ibm.com>
>>> ---
>>> hw/ppc/spapr_rtas.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++
>>> include/hw/ppc/spapr.h | 8 ++++
>>> 2 files changed, 98 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
>>> index 02ddbf9..1135d2b 100644
>>> --- a/hw/ppc/spapr_rtas.c
>>> +++ b/hw/ppc/spapr_rtas.c
>>> @@ -277,6 +277,91 @@ static void rtas_ibm_set_system_parameter(PowerPCCPU *cpu,
>>> rtas_st(rets, 0, ret);
>>> }
>>>
>>> +static void rtas_ibm_nmi_register(PowerPCCPU *cpu,
>>> + sPAPREnvironment *spapr,
>>> + uint32_t token, uint32_t nargs,
>>> + target_ulong args,
>>> + uint32_t nret, target_ulong rets)
>>> +{
>>> + int i;
>>> + uint32_t branch_inst = 0x48000002;
>>> + target_ulong guest_machine_check_addr;
>>> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>>> + /*
>>> + * Trampoline saves r3 in sprg2 and issues private hcall
>>> + * to request qemu to build error log. QEMU builds the
>>> + * error log, copies to rtas-blob and returns the address.
>>> + * The initial 16 bytes in rtas-blob consists of saved srr0
>>> + * and srr1 which we restore and pass on the actual error
>>> + * log address to OS handled mcachine check notification
>>> + * routine
>>> + */
>>> + uint32_t trampoline[] = {
>>> + 0x7c7243a6, /* mtspr SPRN_SPRG2,r3 */
>>> + 0x38600000, /* li r3,0 */
>>> + /* 0xf004 is the KVMPPC_H_REPORT_ERR private HCALL */
>>> + 0x6063f004, /* ori r3,r3,f004 */
>>> + /* Issue H_CALL */
>>> + 0x44000022, /* sc 1 */
>>> + 0x7c9243a6, /* mtspr r4 sprg2 */
>>> + 0xe8830000, /* ld r4, 0(r3) */
>>> + 0x7c9a03a6, /* mtspr r4, srr0 */
>>> + 0xe8830008, /* ld r4, 8(r3) */
>>> + 0x7c9b03a6, /* mtspr r4, srr1 */
>>> + 0x38630010, /* addi r3,r3,16 */
>>> + 0x7c9242a6, /* mfspr r4 sprg2 */
>>> + 0x48000002, /* Branch to address registered
>>> + * by OS. The branch address is
>>> + * patched below */
>>> + 0x48000000, /* b . */
>>
>> So how about we just completely change the layout of the RTAS blob?
>>
>> Imagine something like the following (completely untested):
>>
>> ----
>>
>> /**** index table ****/
>> .long rtas_entry
>> .long nmi_register
>> .long nmi_register_final_branch
>> .long nmi_data
>>
>> /**** RTAS handling code ****/
>> .align 1024
>> rtas_entry:
>> ...
>> nmi_register:
>> ...
>> nmi_register_final_branch:
>> ba .
>>
>> /**** RTAS data regions ****/
>> .align 4096
>> nmi_data:
>> .long 0
>> .align 4096
>>
>> ----
>>
>> With this we should be able to have a nice hybrid between easily tunable
>> asm code and an easy to load and handle blob.
>
> Sorry, I was out of office hence could not respond.
>
> Yes, even I prefer something like this.
>
> BTB, did you intend to have this in spapr-rtas.S? The spapr-rtas.S is
> compiled into a binary and is read into spapr->rtas_blob. If we want to
> have rtas-blob layout something similar to above then we may need to
> link the object file of spapr-rtas.S to QEMU so that the symbols in
> "index table" and other places could be resolved inside QEMU.
>
> If this is fine I will include it in v3.
You can't link against the object file with QEMU, since QEMU could be
executed on an x86 machine which can't compile the rtas blob.
In my proposal above, you would maintain a table of entry points at well
known locations in the binary blob (starting from 0 is probably the
easiest).
Alex
next prev parent reply other threads:[~2014-10-06 9:40 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-25 13:45 [Qemu-devel] [PATCH 0/5] target-ppc: Add FWNMI support in QEMU for powerKVM guests Aravinda Prasad
2014-08-25 13:45 ` [Qemu-devel] [PATCH 1/5] target-ppc: Extend rtas-blob Aravinda Prasad
2014-08-26 5:38 ` David Gibson
2014-08-26 6:34 ` Aravinda Prasad
2014-08-26 7:24 ` David Gibson
2014-08-28 10:40 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 18:20 ` Aravinda Prasad
2014-08-28 22:18 ` Alexander Graf
2014-08-28 22:25 ` Benjamin Herrenschmidt
2014-08-29 0:40 ` Alexander Graf
2014-08-29 1:06 ` Benjamin Herrenschmidt
2014-08-29 1:33 ` Alexander Graf
2014-08-29 2:42 ` Benjamin Herrenschmidt
2014-08-29 3:46 ` David Gibson
2014-08-29 3:47 ` David Gibson
2014-09-01 7:46 ` [Qemu-devel] " Alexey Kardashevskiy
2014-09-01 11:23 ` Aravinda Prasad
2014-09-02 4:09 ` Alexey Kardashevskiy
2014-09-02 5:25 ` Aravinda Prasad
2014-09-02 5:49 ` Alexey Kardashevskiy
2014-09-02 5:56 ` Aravinda Prasad
2014-09-02 6:34 ` Alexey Kardashevskiy
2014-09-02 7:07 ` Aravinda Prasad
2014-09-02 8:40 ` Alexey Kardashevskiy
2014-09-02 9:30 ` Aravinda Prasad
2014-09-02 13:17 ` Alexey Kardashevskiy
2014-08-25 13:45 ` [Qemu-devel] [PATCH 2/5] target-ppc: Register and handle HCALL to receive updated RTAS region Aravinda Prasad
2014-08-26 5:39 ` David Gibson
2014-08-26 6:15 ` Benjamin Herrenschmidt
2014-08-26 7:24 ` David Gibson
2014-08-26 20:05 ` Benjamin Herrenschmidt
2014-08-25 13:45 ` [Qemu-devel] [PATCH 3/5] target-ppc: Build error log Aravinda Prasad
2014-08-26 5:47 ` David Gibson
2014-08-26 6:40 ` Aravinda Prasad
2014-08-27 9:50 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 6:12 ` Aravinda Prasad
2014-08-28 8:36 ` Alexander Graf
2014-08-28 10:21 ` Benjamin Herrenschmidt
2014-08-28 10:29 ` Alexander Graf
2014-08-28 10:33 ` Benjamin Herrenschmidt
2014-08-28 10:34 ` Benjamin Herrenschmidt
2014-08-28 17:17 ` Aravinda Prasad
2014-08-28 20:07 ` Benjamin Herrenschmidt
2014-08-30 8:06 ` Aravinda Prasad
2014-08-25 13:45 ` [Qemu-devel] [PATCH 4/5] target-ppc: Handle ibm, nmi-register RTAS call Aravinda Prasad
2014-08-26 6:02 ` David Gibson
2014-08-26 6:57 ` Aravinda Prasad
2014-08-27 10:37 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 6:38 ` Aravinda Prasad
2014-08-28 8:37 ` Alexander Graf
2014-08-28 13:06 ` Tom Musta
2014-08-28 13:11 ` Alexander Graf
2014-08-28 17:42 ` Aravinda Prasad
2014-08-28 22:16 ` Alexander Graf
2014-08-30 8:08 ` Aravinda Prasad
2014-09-04 8:25 ` Aravinda Prasad
2014-09-04 13:09 ` Alexander Graf
2014-09-04 13:49 ` Aravinda Prasad
2014-09-05 8:46 ` Alexander Graf
2014-09-05 8:52 ` Aravinda Prasad
2014-09-07 20:47 ` Alexander Graf
2014-09-26 3:58 ` Alexey Kardashevskiy
2014-10-06 6:32 ` Aravinda Prasad
2014-10-06 9:40 ` Alexander Graf [this message]
2014-10-06 11:01 ` Aravinda Prasad
2014-08-25 13:45 ` [Qemu-devel] [PATCH 5/5] target-ppc: Handle cases when multi-processors get machine-check Aravinda Prasad
2014-08-26 6:04 ` David Gibson
2014-08-26 7:04 ` Aravinda Prasad
2014-08-27 10:40 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-08-28 6:56 ` Aravinda Prasad
2014-08-28 8:39 ` Alexander Graf
2014-08-28 8:42 ` Alexander Graf
2014-08-28 17:45 ` Aravinda Prasad
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