From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40105) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XbCXk-0004zh-R4 for qemu-devel@nongnu.org; Mon, 06 Oct 2014 13:58:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XbCXg-0001ev-KM for qemu-devel@nongnu.org; Mon, 06 Oct 2014 13:57:56 -0400 Received: from mail-pd0-x236.google.com ([2607:f8b0:400e:c02::236]:49382) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XbCXg-0001eW-B6 for qemu-devel@nongnu.org; Mon, 06 Oct 2014 13:57:52 -0400 Received: by mail-pd0-f182.google.com with SMTP id y10so3656445pdj.27 for ; Mon, 06 Oct 2014 10:57:49 -0700 (PDT) Message-ID: <5432D81A.2080200@gmail.com> Date: Mon, 06 Oct 2014 10:57:46 -0700 From: Sergey Fedorov MIME-Version: 1.0 References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> <1412113785-21525-3-git-send-email-greg.bellows@linaro.org> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Greg Bellows Cc: "Edgar E. Iglesias" , Sergey Fedorov , QEMU Developers , Fabian Aggeler On 06.10.2014 07:56, Peter Maydell wrote: > On 30 September 2014 22:49, Greg Bellows wrote: >> From: Fabian Aggeler >> >> arm_is_secure() function allows to determine CPU security state >> if the CPU implements Security Extensions/EL3. >> arm_is_secure_below_el3() returns true if CPU is in secure state >> below EL3. >> >> Signed-off-by: Sergey Fedorov >> Signed-off-by: Fabian Aggeler >> Signed-off-by: Greg Bellows >> --- >> target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 38 insertions(+) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index 81fffd2..10afef0 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -753,6 +753,44 @@ static inline int arm_feature(CPUARMState *env, int feature) >> return (env->features & (1ULL << feature)) != 0; >> } >> >> + >> +/* Return true if exception level below EL3 is in secure state */ >> +static inline bool arm_is_secure_below_el3(CPUARMState *env) >> +{ >> +#if !defined(CONFIG_USER_ONLY) >> + if (arm_feature(env, ARM_FEATURE_EL3)) { >> + return !(env->cp15.scr_el3 & SCR_NS); >> + } else if (arm_feature(env, ARM_FEATURE_EL2)) { >> + return false; >> + } else { >> + /* IMPDEF: QEMU defaults to non-secure */ >> + return false; > I would be happy to fold both these identical 'return false' > cases together and have a comment that it's only IMPDEF > if EL2 isn't implemented. > >> + } >> +#else >> + return false; >> +#endif >> +} >> + >> +/* Return true if the processor is in secure state */ >> +static inline bool arm_is_secure(CPUARMState *env) >> +{ >> +#if !defined(CONFIG_USER_ONLY) >> + if (arm_feature(env, ARM_FEATURE_EL3)) { >> + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { >> + /* CPU currently in Aarch64 state and EL3 */ > Nit: "AArch64" with two capital 'A's (here and elsewhere). > >> + return true; >> + } else if (!env->aarch64 && >> + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { >> + /* CPU currently in Aarch32 state and monitor mode */ >> + return true; >> + } >> + } >> + return arm_is_secure_below_el3(env); >> +#else >> + return false; >> +#endif >> +} > I checked your git tree and we don't actually use > arm_is_secure_below_el3() anywhere except in > arm_is_secure(), do we? That suggests to me we should > just fold the two functions together. > > Can these functions live in internals.h rather than cpu.h? > (The difference is that internals.h is restricted to only > target-arm/ code whereas cpu.h is auto-included for a much > wider set of files.) Probably arm_is_secure() would be used by ARM GIC emulation until there is no better way to determine memory transaction NS tag. > > thanks > -- PMM