From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XblyJ-0003BU-R5 for qemu-devel@nongnu.org; Wed, 08 Oct 2014 03:47:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XblyD-0004ah-Ri for qemu-devel@nongnu.org; Wed, 08 Oct 2014 03:47:43 -0400 Received: from mail-wi0-x22b.google.com ([2a00:1450:400c:c05::22b]:50243) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XblyD-0004aZ-LC for qemu-devel@nongnu.org; Wed, 08 Oct 2014 03:47:37 -0400 Received: by mail-wi0-f171.google.com with SMTP id em10so9833741wid.16 for ; Wed, 08 Oct 2014 00:47:36 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <5434EC14.5060806@redhat.com> Date: Wed, 08 Oct 2014 09:47:32 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1412711059-12524-1-git-send-email-wei@redhat.com> <543453D9.8020706@redhat.com> <54345843.8070703@redhat.com> <54345CC8.8050806@redhat.com> <54348850.9080808@redhat.com> In-Reply-To: <54348850.9080808@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 1/1] target-i386: prevent users from setting threads>1 for AMD CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Wei Huang , afaerber@suse.de Cc: qemu-devel@nongnu.org Il 08/10/2014 02:41, Wei Huang ha scritto: > I am OK with either way. The key question is: should QEMU presents > CPUIDs strictly as specified by the command line or QEMU can tweak a > little bit on behalf of end-users? For instance, if end-users say "-smp > 8,cores=2,threads=2,sockets=2", they meant "two socket, each has two > 2-hyperthread cores". Current QEMU will convert CPUID as "two socket, > each has 4 cores". My patch will forbid the tweaking... Understood---it actually looks like it was intentional: commit 400281af34e5ee6aa9f5496b53d8f82c6fef9319 Author: Andre Przywara Date: Wed Aug 19 15:42:42 2009 +0200 set CPUID bits to present cores and threads topology Controlled by the enhanced -smp option set the CPUID bits to present the guest the desired topology. This is vendor specific, but (with the exception of the CMP_LEGACY bit) not conflicting, so we set all bits everytime. There is no real multithreading support for AMD CPUs, so report cores instead. Signed-off-by: Andre Przywara Signed-off-by: Anthony Liguori Paolo