From: Christopher Covington <cov@codeaurora.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH] target-arm: Correct sense of the DCZID DZP bit
Date: Fri, 10 Oct 2014 13:23:47 -0400 [thread overview]
Message-ID: <54381623.1070804@codeaurora.org> (raw)
In-Reply-To: <1412959792-20708-1-git-send-email-peter.maydell@linaro.org>
On 10/10/2014 12:49 PM, Peter Maydell wrote:
> The DZP bit in the DCZID system register should be set if
> the control bits which prohibit use of the DC ZVA instruction
> have been set (it stands for Data Zero Prohibited). However
> we had the sense of the test inverted; fix this so that the
> bit reads correctly.
>
> To avoid this regressing the behaviour of the user-mode
> emulator, we must set the DZE bit in the SCTLR for that
> config so that userspace continues to see DZP as zero (it
> was getting the correct result by accident previously).
>
> Reported-by: Christopher Covington <cov@codeaurora.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/cpu.c | 4 ++--
> target-arm/helper.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index edfd586..28e2701 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -102,8 +102,8 @@ static void arm_cpu_reset(CPUState *s)
> env->aarch64 = 1;
> #if defined(CONFIG_USER_ONLY)
> env->pstate = PSTATE_MODE_EL0t;
> - /* Userspace expects access to CTL_EL0 and the cache ops */
> - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
> + /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
> + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
> /* and to the FP/Neon instructions */
> env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
> #else
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 2669e15..904f101 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2018,7 +2018,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
> int dzp_bit = 1 << 4;
>
> /* DZP indicates whether DC ZVA access is allowed */
> - if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
> + if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) {
> dzp_bit = 0;
> }
> return cpu->dcz_blocksize | dzp_bit;
>
Reviewed-by: Christopher Covington <cov@codeaurora.org>
Thanks Peter!
Christopher
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
prev parent reply other threads:[~2014-10-10 17:24 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-10 16:49 [Qemu-devel] [PATCH] target-arm: Correct sense of the DCZID DZP bit Peter Maydell
2014-10-10 17:23 ` Christopher Covington [this message]
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