From: Leon Alrae <leon.alrae@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: james.hogan@imgtec.com, aurelien@aurel32.net, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families
Date: Tue, 14 Oct 2014 12:40:17 +0100 [thread overview]
Message-ID: <543D0BA1.3000909@imgtec.com> (raw)
In-Reply-To: <543BD5AC.2030106@imgtec.com>
Hi Yongbok,
On 13/10/2014 14:37, Yongbok Kim wrote:
>> + OPC_PCREL = (0x3B << 26),
>> +};
>> +
>> +/* PC-relative address computation / loads */
>> +#define MASK_OPC_PCREL_TOP2BITS(op) (MASK_OP_MAJOR(op) | (op & (3 <<
>> 19)))
>> +#define MASK_OPC_PCREL_TOP5BITS(op) (MASK_OP_MAJOR(op) | (op & (0x1f
>> << 16)))
>
> There must be better name for this macro.
> It confused me that was looking like 31 and 30 bits.
> Just naming though...
TOP2BITS and TOP5BITS are referring to "TTTTT" bits. R6 PC-relative
family encoding: 111011.rs.TTTTT.imm16
Instructions:
111011.rs.00.<-----imm19> ADDIUPC
111011.rs.01.<----disp19> LWPC
111011.rs.10.<----disp19> LWUPC
111011.rs.110.<---disp18> LDPC
111011.rs.1110.<---imm17> reserved
111011.rs.11110.<--imm16> AUIPC
111011.rs.11111.<--imm16> ALUIPC
I couldn't come up with better name having reasonable length, any
suggestions are welcome.
Thanks,
Leon
next prev parent reply other threads:[~2014-10-14 11:40 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-08 10:55 [Qemu-devel] [PATCH v4 00/21] target-mips: add MIPS64R6 Instruction Set support Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 01/21] target-mips: define ISA_MIPS64R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 02/21] target-mips: signal RI Exception on instructions removed in R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 03/21] target-mips: add SELEQZ and SELNEZ instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 04/21] target-mips: move LL and SC instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 05/21] target-mips: extract decode_opc_special* from decode_opc Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 06/21] target-mips: split decode_opc_special* into *_r6 and *_legacy Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 07/21] target-mips: signal RI Exception on DSP and Loongson instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 08/21] target-mips: move PREF, CACHE, LLD and SCD instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 09/21] target-mips: redefine Integer Multiply and Divide instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 10/21] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 12/21] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 13/21] target-mips: add compact and CP1 branches Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families Leon Alrae
2014-10-13 13:37 ` Yongbok Kim
2014-10-14 11:40 ` Leon Alrae [this message]
2014-11-12 21:07 ` Paolo Bonzini
2014-11-13 10:39 ` Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 15/21] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 16/21] target-mips: add new Floating Point instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 17/21] target-mips: add new Floating Point Comparison instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 19/21] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 20/21] mips_malta: update malta's pseudo-bootloader - replace JR with JALR Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 21/21] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA Leon Alrae
2014-10-14 9:05 ` Yongbok Kim
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