From: Leon Alrae <leon.alrae@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 7/9] target-mips: add TLBINV support
Date: Thu, 16 Oct 2014 14:03:37 +0100 [thread overview]
Message-ID: <543FC229.9010409@imgtec.com> (raw)
In-Reply-To: <543FA37F.8080804@imgtec.com>
On 16/10/2014 11:52, Yongbok Kim wrote:
>> + ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 1;
>
> & 3
>
Yeah, initially I tested TLBINV using mips64r6-generic cpu where
Config4.IE is set to 3, thus it worked...
Thanks,
Leon
next prev parent reply other threads:[~2014-10-16 13:03 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-08 7:57 [Qemu-devel] [PATCH v2 0/9] target-mips: implement features required in MIPS64 Release 6 Leon Alrae
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers Leon Alrae
2014-10-14 13:59 ` Yongbok Kim
2014-10-20 12:54 ` Leon Alrae
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 2/9] softmmu: provide softmmu access type enum Leon Alrae
2014-07-08 13:00 ` Peter Maydell
2014-07-08 16:08 ` Leon Alrae
2014-07-08 16:12 ` Peter Maydell
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 3/9] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-10-14 15:55 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 4/9] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-10-15 12:24 ` Yongbok Kim
2014-10-24 14:16 ` Leon Alrae
2014-10-24 14:27 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 5/9] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-10-15 15:20 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 6/9] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-10-15 15:39 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 7/9] target-mips: add TLBINV support Leon Alrae
2014-10-16 10:52 ` Yongbok Kim
2014-10-16 13:03 ` Leon Alrae [this message]
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 8/9] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-07-08 12:44 ` James Hogan
2014-07-08 15:56 ` Leon Alrae
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 9/9] target-mips: update cpu_save/cpu_load to support new registers Leon Alrae
2014-10-16 13:06 ` Yongbok Kim
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