From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xjcel-0002yl-Ur for qemu-devel@nongnu.org; Wed, 29 Oct 2014 19:28:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xjcee-0006pe-Bl for qemu-devel@nongnu.org; Wed, 29 Oct 2014 19:27:59 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:40260) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xjcee-0006pT-5y for qemu-devel@nongnu.org; Wed, 29 Oct 2014 19:27:52 -0400 Message-ID: <545177EF.1090402@imgtec.com> Date: Wed, 29 Oct 2014 23:27:43 +0000 From: Leon Alrae MIME-Version: 1.0 References: <1414546928-54642-1-git-send-email-yongbok.kim@imgtec.com> <1414546928-54642-12-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1414546928-54642-12-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 11/20] target-mips: add MSA I5 format instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 29/10/14 01:41, Yongbok Kim wrote: > + uint8_t df = (ctx->opcode >> 21) & 0x3; > + int64_t s5 = (ctx->opcode >> 16) & 0x1f; > + s5 = (s5 << 59) >> 59; /* sign extend s5 to 64 bits*/ Mixed declarations and code are not allowed. This issue occurs also in subsequent patches (12, 15, 17, 18) in this series. You may also consider using sextract() for s5. > + uint8_t u5 = (ctx->opcode >> 16) & 0x1f; > + uint8_t ws = (ctx->opcode >> 11) & 0x1f; > + uint8_t wd = (ctx->opcode >> 6) & 0x1f; > + > + TCGv_i32 tdf = tcg_const_i32(df); > + TCGv_i32 twd = tcg_const_i32(wd); > + TCGv_i32 tws = tcg_const_i32(ws); > + TCGv_i64 tu5 = tcg_const_i64(u5); > + TCGv_i64 ts5 = tcg_const_i64(s5); One of above tcg variable is redundant as tu5 and ts5 are never used together. Have you considered to have just one tcg variable initialized later - in case blocks - with appropriate value? You already did this for ts10 in case OPC_LDI_df. > + > + switch (MASK_MSA_I5(opcode)) { > + case OPC_ADDVI_df: > + gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, tu5); > + break; > + case OPC_SUBVI_df: > + gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, tu5); > + break; > + case OPC_MAXI_S_df: > + gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, ts5); > + break; > + case OPC_MAXI_U_df: > + gen_helper_msa_maxi_u_df(cpu_env, tdf, twd, tws, tu5); > + break; > + case OPC_MINI_S_df: > + gen_helper_msa_mini_s_df(cpu_env, tdf, twd, tws, ts5); > + break; > + case OPC_MINI_U_df: > + gen_helper_msa_mini_u_df(cpu_env, tdf, twd, tws, tu5); > + break; > + case OPC_CEQI_df: > + gen_helper_msa_ceqi_df(cpu_env, tdf, twd, tws, ts5); > + break; > + case OPC_CLTI_S_df: > + gen_helper_msa_clti_s_df(cpu_env, tdf, twd, tws, ts5); > + break; > + case OPC_CLTI_U_df: > + gen_helper_msa_clti_u_df(cpu_env, tdf, twd, tws, tu5); > + break; > + case OPC_CLEI_S_df: > + gen_helper_msa_clei_s_df(cpu_env, tdf, twd, tws, ts5); > + break; > + case OPC_CLEI_U_df: > + gen_helper_msa_clei_u_df(cpu_env, tdf, twd, tws, tu5); > + break; > + case OPC_LDI_df: > + { > + int64_t s10 = (ctx->opcode >> 11) & 0x3ff; > + s10 = (s10 << 54) >> 54; /* sign extend s10 to 64 bits*/ Mixed declarations and code > + > + TCGv_i32 ts10 = tcg_const_i32(s10); > + gen_helper_msa_ldi_df(cpu_env, tdf, twd, ts10); > + tcg_temp_free_i32(ts10);