From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xjg0z-00045A-SG for qemu-devel@nongnu.org; Wed, 29 Oct 2014 23:03:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xjg0q-0004OO-Sz for qemu-devel@nongnu.org; Wed, 29 Oct 2014 23:03:09 -0400 Received: from mail-pd0-x22d.google.com ([2607:f8b0:400e:c02::22d]:41972) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjfuL-0002Z7-4F for qemu-devel@nongnu.org; Wed, 29 Oct 2014 22:56:17 -0400 Received: by mail-pd0-f173.google.com with SMTP id v10so4209720pde.18 for ; Wed, 29 Oct 2014 19:56:15 -0700 (PDT) Sender: Richard Henderson Message-ID: <5451A8CC.9080205@twiddle.net> Date: Wed, 29 Oct 2014 19:56:12 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1414588941-845-1-git-send-email-kbastian@mail.uni-paderborn.de> <1414588941-845-6-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1414588941-845-6-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 5/5] target-tricore: Add instructions of RC opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 10/29/2014 06:22 AM, Bastian Koppelmann wrote: > + } else if (shift_count > 0) { > + low = tcg_temp_new(); > + high = tcg_temp_new(); > + > + tcg_gen_andi_tl(low, r1, 0xffff); > + tcg_gen_andi_tl(high, r1, 0xffff0000); > + tcg_gen_shli_tl(low, low, shift_count); > + tcg_gen_shli_tl(ret, high, shift_count); > + tcg_gen_deposit_tl(ret, ret, low, 0, 16); You don't need to mask low here, > + > + tcg_temp_free(low); > + tcg_temp_free(high); > + } else { > + low = tcg_temp_new(); > + high = tcg_temp_new(); > + > + tcg_gen_ext16s_tl(low, r1); > + tcg_gen_andi_tl(high, r1, 0xffff0000); > + tcg_gen_sari_tl(low, low, -shift_count); > + tcg_gen_sari_tl(ret, high, -shift_count); > + tcg_gen_deposit_tl(ret, ret, low, 0, 16); Or high here, since the deposit takes care of that, and you're shifting away from the mask. r~