From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XkEKL-0005mE-Oh for qemu-devel@nongnu.org; Fri, 31 Oct 2014 11:42:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjrtA-0005WB-As for qemu-devel@nongnu.org; Thu, 30 Oct 2014 11:43:57 -0400 Received: from mail-qg0-x230.google.com ([2607:f8b0:400d:c04::230]:49125) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjrtA-0005W5-6B for qemu-devel@nongnu.org; Thu, 30 Oct 2014 11:43:52 -0400 Received: by mail-qg0-f48.google.com with SMTP id q108so4109651qgd.7 for ; Thu, 30 Oct 2014 08:43:51 -0700 (PDT) Sender: Richard Henderson Message-ID: <54525CB2.1080709@twiddle.net> Date: Thu, 30 Oct 2014 08:43:46 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1414684746-13771-1-git-send-email-kbastian@mail.uni-paderborn.de> <1414684746-13771-6-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1414684746-13771-6-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 5/5] target-tricore: Add instructions of RC opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 10/30/2014 08:59 AM, Bastian Koppelmann wrote: > Add instructions of RC opcode format. > Add helper for mul, sha, absdif with signed saturation on overflow. > Add helper for add, sub, mul with unsigned saturation on overflow. > Add microcode generator functions: > * gen_add_CC, which calculates the carry bit. > * gen_addc_CC, which adds the carry bit to the add and calculates the carry bit. > * gen_absdif, which calculates the absolute difference. > * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg. > * gen_sh_hi, which shifts two 16bit words in one reg. > * gen_sha_hi, which does a arithmetic shift on two 16bit words. > * gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb. > * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs > with the lsb of the result. > * gen_eqany_bi/hi, which checks ever byte/hword on equality. > > Signed-off-by: Bastian Koppelmann > --- > v1 -> v2: > - gen_sha_hi: Remove mask for low in case shift_count > 0, since deposit handles that. > - gen_sha_hi: Remove mask for high in case shift <= 0, since deposit handles that. Reviewed-by: Richard Henderson r~