From: Leon Alrae <leon.alrae@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: qemu-devel@nongnu.org, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support
Date: Sat, 1 Nov 2014 19:27:28 +0000 [thread overview]
Message-ID: <54553420.7030508@imgtec.com> (raw)
In-Reply-To: <5450F1EA.3060304@imgtec.com>
Hi Yongbok,
On 29/10/14 13:55, Yongbok Kim wrote:
> On 24/10/2014 13:42, Leon Alrae wrote:
>> case EXCP_TLBRI:
>> cause = 19;
>> + update_badinstr = 1;
>> goto set_EPC;
>> case EXCP_TLBXI:
>> cause = 20;
>
> TLBXI requires updating the register.
TLBXI exception can be generated by instruction fetch or MIPS16
PC-relative load. IIUC if TLBXI is caused by instruction fetch the value
stored in BadInstr is unpredictable as valid instruction word is not
available (the same case as TLB Refill - Instruction Fetch). Therefore
in context of Release 6 the implementation is correct. As far as MIPS16
is concerned, this is similar limitation which we discussed for patch #4
(i.e. MIPS16 PC-relative load should ignore RI bit).
Regards,
Leon
next prev parent reply other threads:[~2014-11-01 19:28 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-24 12:42 [Qemu-devel] [PATCH v3 00/15] target-mips: add features required in MIPS64R6 Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 01/15] target-mips: add KScratch registers Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 02/15] softmmu: provide softmmu access type enum Leon Alrae
2014-10-24 13:59 ` Thomas Huth
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 03/15] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 04/15] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-10-24 14:29 ` Yongbok Kim
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 05/15] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 06/15] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 07/15] target-mips: add TLBINV support Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-10-29 13:55 ` Yongbok Kim
2014-11-01 19:27 ` Leon Alrae [this message]
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 09/15] target-mips: update cpu_save/cpu_load to support new registers Leon Alrae
2014-10-29 14:02 ` Yongbok Kim
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 10/15] target-mips: add Config5.SBRI Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 11/15] target-mips: implement forbidden slot Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 12/15] target-mips: CP0_Status.CU0 no longer allows the user to access CP0 Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 13/15] target-mips: add restrictions for possible values in registers Leon Alrae
2014-10-29 11:04 ` Yongbok Kim
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 14/15] target-mips: correctly handle access to unimplemented CP0 register Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 15/15] target-mips: enable features in MIPS64R6-generic CPU Leon Alrae
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