From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xl1R0-0006zm-JG for qemu-devel@nongnu.org; Sun, 02 Nov 2014 15:07:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xl1Qv-00059F-GQ for qemu-devel@nongnu.org; Sun, 02 Nov 2014 15:07:34 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:61361) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xl1Qv-00058e-8R for qemu-devel@nongnu.org; Sun, 02 Nov 2014 15:07:29 -0500 Message-ID: <54568ED2.3000008@imgtec.com> Date: Sun, 2 Nov 2014 20:06:42 +0000 From: Leon Alrae MIME-Version: 1.0 References: <1414819733-30765-1-git-send-email-yongbok.kim@imgtec.com> <1414819733-30765-20-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1414819733-30765-20-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 19/19] target-mips: add MSA support to mips32r5-generic List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On 01/11/14 05:28, Yongbok Kim wrote: > add MSA support to mips32r5-generic core definition > > Signed-off-by: Yongbok Kim > --- > target-mips/translate_init.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c > index 8fb8bf8..0b4b597 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -358,7 +358,7 @@ static const mips_def_t mips_defs[] = > (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | > (1 << CP0C1_CA), > .CP0_Config2 = MIPS_CONFIG2, > - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), > + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), > .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), > .CP0_Config4_rw_bitmask = 0, > .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), > @@ -376,7 +376,7 @@ static const mips_def_t mips_defs[] = > (0x93 << FCR0_PRID), > .SEGBITS = 32, > .PABITS = 32, > - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, > + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, > .mmu_type = MMU_TYPE_R4000, > }, > #if defined(TARGET_MIPS64) Reviewed-by: Leon Alrae