From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60345) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlZu1-0006a6-S8 for qemu-devel@nongnu.org; Tue, 04 Nov 2014 03:55:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlZtx-0008Rf-HS for qemu-devel@nongnu.org; Tue, 04 Nov 2014 03:55:49 -0500 Received: from lhrrgout.huawei.com ([194.213.3.17]:35947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlZtx-0008QE-9B for qemu-devel@nongnu.org; Tue, 04 Nov 2014 03:55:45 -0500 Message-ID: <54589473.5040804@huawei.com> Date: Tue, 4 Nov 2014 09:55:15 +0100 From: Claudio Fontana MIME-Version: 1.0 References: <1414524244-20316-1-git-send-email-peter.maydell@linaro.org> <1414524244-20316-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1414524244-20316-6-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 5/5] target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: patches@linaro.org Reviewed-by: Claudio Fontana On 28.10.2014 20:24, Peter Maydell wrote: > Refactor to avoid passing a CPUARMState * to disas_arm_insn(). To do this > we move the "read insn from memory" code to the callsite and pass the > insn to the function instead. > > Signed-off-by: Peter Maydell > --- > target-arm/translate.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 9e2dda2..932fa03 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7560,18 +7560,15 @@ static void gen_srs(DisasContext *s, > tcg_temp_free_i32(addr); > } > > -static void disas_arm_insn(CPUARMState * env, DisasContext *s) > +static void disas_arm_insn(DisasContext *s, unsigned int insn) > { > - unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; > + unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; > TCGv_i32 tmp; > TCGv_i32 tmp2; > TCGv_i32 tmp3; > TCGv_i32 addr; > TCGv_i64 tmp64; > > - insn = arm_ldl_code(env, s->pc, s->bswap_code); > - s->pc += 4; > - > /* M variants do not implement ARM mode. */ > if (arm_dc_feature(s, ARM_FEATURE_M)) { > goto illegal_op; > @@ -11199,7 +11196,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, > } > } > } else { > - disas_arm_insn(env, dc); > + unsigned int insn = arm_ldl_code(env, dc->pc, dc->bswap_code); > + dc->pc += 4; > + disas_arm_insn(dc, insn); > } > > if (dc->condjmp && !dc->is_jmp) { > -- Claudio Fontana Server Virtualization Architect Huawei Technologies Duesseldorf GmbH Riesstraße 25 - 80992 München office: +49 89 158834 4135 mobile: +49 15253060158