From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38208) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlgVP-0002lX-BU for qemu-devel@nongnu.org; Tue, 04 Nov 2014 10:58:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlgVJ-0006oN-8q for qemu-devel@nongnu.org; Tue, 04 Nov 2014 10:58:51 -0500 Received: from plane.gmane.org ([80.91.229.3]:57087) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlgVJ-0006oF-3M for qemu-devel@nongnu.org; Tue, 04 Nov 2014 10:58:45 -0500 Received: from list by plane.gmane.org with local (Exim 4.69) (envelope-from ) id 1XlgVH-0005hs-DM for qemu-devel@nongnu.org; Tue, 04 Nov 2014 16:58:43 +0100 Received: from net-37-117-142-149.cust.vodafonedsl.it ([37.117.142.149]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Tue, 04 Nov 2014 16:58:43 +0100 Received: from pbonzini by net-37-117-142-149.cust.vodafonedsl.it with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Tue, 04 Nov 2014 16:58:43 +0100 From: Paolo Bonzini Date: Tue, 04 Nov 2014 16:58:32 +0100 Message-ID: <5458F7A8.30103@redhat.com> References: <1415044877-17300-1-git-send-email-tommusta@gmail.com> <1415044877-17300-3-git-send-email-tommusta@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit In-Reply-To: <1415044877-17300-3-git-send-email-tommusta@gmail.com> Subject: Re: [Qemu-devel] [PATCH 2/7] target-ppc: Introduce gen_set_cr1_from_fpscr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: agraf@suse.de What tree are these patches based on? Alex's tree already has a commit 15a6b218c221a34b12e81790f427efec3108dce9 Author: Paolo Bonzini Date: Thu Aug 28 19:15:07 2014 +0200 ppc: rename gen_set_cr6_from_fpscr It sets CR1, not CR6 (and the spec agrees). Signed-off-by: Paolo Bonzini Reviewed-by: Tom Musta Tested-by: Tom Musta Signed-off-by: Alexander Graf that conflicts (semantically) with this. Paolo On 03/11/2014 21:01, Tom Musta wrote: > The Power ISA supports a mode in many floating point instructions whereby > the Condition Register field 1 (CR[1]) receives a copy of the Floating > Point Status (FPSCR) bits 32:35, also known as FX, FEX VX and OX. > > The existing QEMU code is mostly wrong -- CR[1] is set to the Floating > Point Condition Code (FPSCR[FPCC]). Furthermore, this code is buried > inside the code that generates the FPSCR[FPRF] code, which is awkward. > > Introduce a new generator utility that correctly sets CR[1] from the > FPSCR bits. Subsequent patches will correct various segments of > the defective code and will clean up the gen_compute_fprf() > utility. > > Signed-off-by: Tom Musta > --- > target-ppc/translate.c | 8 ++++++++ > 1 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index d03daea..7775bf4 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -249,6 +249,14 @@ static inline void gen_reset_fpstatus(void) > gen_helper_reset_fpstatus(cpu_env); > } > > +static inline void gen_set_cr1_from_fpscr(void) > +{ > + TCGv_i32 t0 = tcg_temp_new_i32(); > + tcg_gen_trunc_tl_i32(t0, cpu_fpscr); > + tcg_gen_shri_i32(cpu_crf[1], t0, 28); > + tcg_temp_free_i32(t0); > +} > + > static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) > { > TCGv_i32 t0 = tcg_temp_new_i32(); >