From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42599) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlliC-0002mP-4m for qemu-devel@nongnu.org; Tue, 04 Nov 2014 16:32:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xlli4-0002q1-Lw for qemu-devel@nongnu.org; Tue, 04 Nov 2014 16:32:24 -0500 Received: from cantor2.suse.de ([195.135.220.15]:57828 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xlli4-0002od-FX for qemu-devel@nongnu.org; Tue, 04 Nov 2014 16:32:16 -0500 Message-ID: <545945DD.2030009@suse.de> Date: Tue, 04 Nov 2014 22:32:13 +0100 From: Alexander Graf MIME-Version: 1.0 References: <1415132365-16759-1-git-send-email-agraf@suse.de> <54594CE5.30505@mail.uni-paderborn.de> In-Reply-To: <54594CE5.30505@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] s390x: Implement SAM{24,31,64} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , rth@twiddle.net Cc: qemu-devel@nongnu.org On 04.11.14 23:02, Bastian Koppelmann wrote: >=20 > On 11/04/2014 08:19 PM, Alexander Graf wrote: >> +static ExitStatus op_sam(DisasContext *s, DisasOps *o) >> +{ >> + int sam =3D s->insn->data; >> + TCGv_i64 tsam =3D tcg_const_i64(sam); >> + >> + /* Overwrite PSW_MASK_64 and PSW_MASK_32 */ >> + tcg_gen_deposit_i64(psw_mask, psw_mask, tsam, 31, 2); >> + >> + tcg_temp_free_i64(tsam); >> + return EXIT_PC_STALE; >> +} >> + > You forgot to zero out bits 64-103 of psw, in case of sam24 and bits > 64-96 in case of sam31. These are the address bits. PSW contains an "addr" and a "mask" field. "addr" is PC, "mask" is similar to MSR on PPC or EFER on x86. Other bits of the code will take care of masking out unused address bits for 31 bit mode (check out fix_address() in mem_helper.c for example). We don't really implent 24bit addressing mode - and I doubt we will in the near future. Today our only target is Linux - and there simply is no 24bit Linux out there ;). > Also you forgot to add 2 (the instruction length) to bits 64-127 of psw This happens automatically. Each instruction carries its length in the first 2 bits, so the instruction walker can automatically increment PC. > or if this is a target of EXECUTE/EXECUTE RELATIVE LONG add 4/6. EXECUTE is tricky. Basically EXECUTE is an instruction that behaves like the instruction that a memory reference points to, but at the location the EXECUTE is actually in. Today, we treat EXECUTE as a very special instruction with only a small number of subinstructions that it handles (namely the ones gcc emits). But thanks a lot for the thorough review :) Alex