Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Leon Alrae <leon.alrae@imgtec.com>]

On 07/11/2014 12:33, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
> 
>> When I've been applying this patch to my mips-next candidate branch for
>> 2.2 I realized that you haven't rebased it onto the recent version where
>> MSA has been added to mips32r5-generic. Now I don't think that having
>> DSP and MSA on one CPU makes sense, therefore what I'm going to do is to
>> change mips32r5-generic part in your patch slightly: instead of setting
>> CP0.Config3.DSP/DSP2P the patch will remove ASE_DSP/DSPR2 insn_flags.
> 
>  I have been working with the current trunk, the change applies 
> correctly there AFAICT.

55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
mips32r5-generic which is not present on your patch.

> 
>  I have no objections to changing mips32r5-generic, it is artificial 
> anyway.  But what do you mean by DSP and MSA on one CPU having no sense, 
> is there a conflict between the two ASEs?

I was considering making mips32r5-generic less artificial and slowly
evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
supports MSA, but doesn't support DSP ASE). Furthermore, none from the
latest MIPS CPUs supports both ASEs.

Regards,
Leon