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From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v4 4/4] target-tricore: Add instructions of RCR opcode format
Date: Fri, 21 Nov 2014 16:29:52 +0100	[thread overview]
Message-ID: <546F5A70.9070802@twiddle.net> (raw)
In-Reply-To: <1416583914-15891-5-git-send-email-kbastian@mail.uni-paderborn.de>

On 11/21/2014 04:31 PM, Bastian Koppelmann wrote:
> Add instructions of RCR opcode format.
> Add helper for madd32/64_ssov and madd32/64_suov.
> Add helper for msub32/64_ssov and msub32/64_suov.
> Add microcode generator function madd/msub for 32bit and 64bit, which calculate a mul and a add/sub.
> OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32.
> 
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> v3 -> v4:
>     - helper madd64_ssov/suov and msub64_ssov/suov now use 64 bit arithmetic for the add. (Thanks alot, Richard!)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

      reply	other threads:[~2014-11-21 15:36 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-21 15:31 [Qemu-devel] [PATCH v4 0/4] Add TriCore RCPW, RCRR, RCRW, RLC and RCR instructions Bastian Koppelmann
2014-11-21 15:31 ` [Qemu-devel] [PATCH v4 1/4] target-tricore: Make TRICORE_FEATURES implying others Bastian Koppelmann
2014-11-21 15:31 ` [Qemu-devel] [PATCH v4 2/4] target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format Bastian Koppelmann
2014-11-21 15:31 ` [Qemu-devel] [PATCH v4 3/4] target-tricore: Add instructions of RLC " Bastian Koppelmann
2014-11-21 15:31 ` [Qemu-devel] [PATCH v4 4/4] target-tricore: Add instructions of RCR " Bastian Koppelmann
2014-11-21 15:29   ` Richard Henderson [this message]

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