From: Leon Alrae <leon.alrae@imgtec.com>
To: "Maciej W. Rozycki" <macro@codesourcery.com>, qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH] target-mips: Output CP0.Config2-5 in the register dump
Date: Tue, 2 Dec 2014 10:42:30 +0000 [thread overview]
Message-ID: <547D9796.6090702@imgtec.com> (raw)
In-Reply-To: <alpine.DEB.1.10.1411180311390.2881@tp.orcam.me.uk>
On 18/11/2014 03:20, Maciej W. Rozycki wrote:
> @@ -19276,6 +19276,10 @@ void mips_cpu_dump_state(CPUState *cs, F
> env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
> cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx "\n",
> env->CP0_Config0, env->CP0_Config1, env->lladdr);
> + cpu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n",
> + env->CP0_Config2, env->CP0_Config3);
> + cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n",
> + env->CP0_Config4, env->CP0_Config5);
Wouldn't it be better to order these registers for example by CP0
Register and Select number rather than putting them at the end? I think
it doesn't matter at the moment as there are just few registers printed
out, but once we start adding more then probably we would like to avoid
having them placed arbitrarily in the output.
Regards,
Leon
next prev parent reply other threads:[~2014-12-02 10:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-18 3:20 [Qemu-devel] [PATCH] target-mips: Output CP0.Config2-5 in the register dump Maciej W. Rozycki
2014-12-02 10:42 ` Leon Alrae [this message]
2014-12-02 11:37 ` Maciej W. Rozycki
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