[Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses

[Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses

[Maciej W. Rozycki]

Fix CP0.Config3.ISAOnExc write accesses on microMIPS processors.  This
bit is mandatory for any processor that implements the microMIPS
instruction set.  This bit is r/w for processors that implement both the
standard MIPS and the microMIPS instruction set.  This bit is r/o and
hardwired to 1 if only the microMIPS instruction set is implemented.

There is no other bit ever writable in CP0.Config3 so defining a
corresponding `CP0_Config3_rw_bitmask' member in `CPUMIPSState' is I
think an overkill.  Therefore make the ability to write the bit rely on
the presence of ASE_MICROMIPS set in the instruction flags.

The read-only case of the microMIPS instruction set being implemented
only can be added when we add support for such a configuration.  We do
not currently have such support, we have no instruction flag that would
control the presence of the standard MIPS instruction set nor any
associated code in instruction decoding.

This change is needed to boot a microMIPS Linux kernel successfully,
otherwise it hangs early on as interrupts are enabled and then the
exception handler invoked loops as its first instruction is interpreted
in the wrong execution mode and triggers another exception right away.
And then over and over again.

We already check the current setting of the CP0.Config3.ISAOnExc in
`set_hflags_for_handler' to set the ISA bit correctly on the exception
handler entry so it is the ability to set it that is missing only.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
Hi,

 I think there isn't anything else to add here as to the change itself. 
I must have been the first one to try a microMIPS Linux kernel on QEMU 
as I had to make a small tweak to Linux configuration too to be able to 
build such a kernel at all that can run on a hardware configuration 
supported by QEMU (Malta specifically; the only system enabled for 
microMIPS configuration in Linux used to be SEAD-3 that in turn we have 
no support for).  I think that's a shame, microMIPS support has been 
there both in QEMU and in Linux for a while now but there you go.

 The good news is with this change in place microMIPS Linux boots to the 
multiuser mode and even survives banging on with GNU toolchain test 
suites.  I'll be using that arrangement for the validation of some of 
the upcoming changes; that should give us reasonable coverage.

 Please note that for this validation I'm using an artificial microMIPS 
processor that also has an FPU implemented, so that our microMIPS FP 
support is correctly validated too (I don't really know if there exists 
any real microMIPS processor that includes an FPU; if so, then it would 
be good to add it to the list our supported configurations).

 Also, FYI, the handler for DMTC0 to Config4 appears to be missing.

 Please apply.

  Maciej

qemu-mips-config3-isaonexc.diff
Index: qemu-git-trunk/target-mips/helper.h
===================================================================
--- qemu-git-trunk.orig/target-mips/helper.h	2014-11-17 04:52:21.000000000 +0000
+++ qemu-git-trunk/target-mips/helper.h	2014-11-17 04:52:25.397682963 +0000
@@ -137,6 +137,7 @@ DEF_HELPER_2(mtc0_ebase, void, env, tl)
 DEF_HELPER_2(mttc0_ebase, void, env, tl)
 DEF_HELPER_2(mtc0_config0, void, env, tl)
 DEF_HELPER_2(mtc0_config2, void, env, tl)
+DEF_HELPER_2(mtc0_config3, void, env, tl)
 DEF_HELPER_2(mtc0_config4, void, env, tl)
 DEF_HELPER_2(mtc0_config5, void, env, tl)
 DEF_HELPER_2(mtc0_lladdr, void, env, tl)
Index: qemu-git-trunk/target-mips/op_helper.c
===================================================================
--- qemu-git-trunk.orig/target-mips/op_helper.c	2014-11-17 04:52:21.000000000 +0000
+++ qemu-git-trunk/target-mips/op_helper.c	2014-11-17 05:05:01.478644569 +0000
@@ -1503,6 +1503,14 @@ void helper_mtc0_config2(CPUMIPSState *e
     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
 }
 
+void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
+{
+    if (env->insn_flags & ASE_MICROMIPS) {
+        env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
+                           (arg1 & (1 << CP0C3_ISA_ON_EXC));
+    }
+}
+
 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
 {
     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
Index: qemu-git-trunk/target-mips/translate.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate.c	2014-11-17 04:52:21.000000000 +0000
+++ qemu-git-trunk/target-mips/translate.c	2014-11-17 04:55:11.909027669 +0000
@@ -5846,8 +5846,10 @@ static void gen_mtc0(DisasContext *ctx, 
             ctx->bstate = BS_STOP;
             break;
         case 3:
-            /* ignored, read only */
+            gen_helper_mtc0_config3(cpu_env, arg);
             rn = "Config3";
+            /* Stop translation as we may have switched the execution mode */
+            ctx->bstate = BS_STOP;
             break;
         case 4:
             gen_helper_mtc0_config4(cpu_env, arg);
@@ -7097,8 +7099,10 @@ static void gen_dmtc0(DisasContext *ctx,
             ctx->bstate = BS_STOP;
             break;
         case 3:
-            /* ignored */
+            gen_helper_mtc0_config3(cpu_env, arg);
             rn = "Config3";
+            /* Stop translation as we may have switched the execution mode */
+            ctx->bstate = BS_STOP;
             break;
         case 4:
             /* currently ignored */

Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses

[Leon Alrae]

On 18/11/2014 03:59, Maciej W. Rozycki wrote:
>  Please note that for this validation I'm using an artificial microMIPS 
> processor that also has an FPU implemented, so that our microMIPS FP 
> support is correctly validated too (I don't really know if there exists 
> any real microMIPS processor that includes an FPU; if so, then it would 
> be good to add it to the list our supported configurations).

FYI, there are real CPUs which support microMIPS and include FPU, for
example microAptivUC.

> qemu-mips-config3-isaonexc.diff

Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>

Re: [Qemu-devel] [PATCH] target-mips: Fix CP0.Config3.ISAOnExc write accesses

[Maciej W. Rozycki]

On Tue, 2 Dec 2014, Leon Alrae wrote:

> >  Please note that for this validation I'm using an artificial microMIPS 
> > processor that also has an FPU implemented, so that our microMIPS FP 
> > support is correctly validated too (I don't really know if there exists 
> > any real microMIPS processor that includes an FPU; if so, then it would 
> > be good to add it to the list our supported configurations).
> 
> FYI, there are real CPUs which support microMIPS and include FPU, for
> example microAptivUC.

 Good to know, thanks, and good to have real hardware as a reference.  
Thanks for your review.

  Maciej